Understanding photonic quantum-logic gates: The road to fault tolerance

Abstract: Fault-tolerant quantum computing requires gates which function correctly despite the presence of errors, and are scalable if the error probability-per-gate is below a threshold value. To date, no method has been described for calculating this probability from measurements on a gate. Here we introduce a technique enabling quantitative benchmarking of quantum-logic gates against fault-tolerance thresholds for any architecture. We demonstrate our technique experimentally using a photonic entangling-gate. The relationship between experimental errors and their quantum logic effect is non-trivial: revealing this relationship requires a comprehensive theoretical model of the quantum-logic gate. We show the first such model for any architecture, and find multi-photon emission--a small effect previously regarded as secondary to mode-mismatch--to be the dominant source of logic error. We show that reducing this will move photonic quantum computing to within striking distance of fault-tolerance.