Development of active edge pixel sensors and four-side buttable modules using vertical integration technologies

Abstract: We present an R&D activity focused on the development of novel modules for the upgrade of the ATLAS pixel system at the High Luminosity LHC (HL-LHC). The modules consist of n-in-p pixel sensors, 100 or 200 $\mu$m thick, produced at VTT (Finland) with an active edge technology, which considerably reduces the dead area at the periphery of the device. The sensors are interconnected with solder bump-bonding to the ATLAS FE-I3 and FE-I4 read-out chips, and characterized with radioactive sources and beam tests at the CERN-SPS and DESY. The results of these measurements will be discussed for devices before and after irradiation up to a fluence of $5\times 10^{15}$ \neqcm. We will also report on the R&D activity to obtain Inter Chip Vias (ICVs) on the ATLAS read-out chip in collaboration with the Fraunhofer Institute EMFT. This step is meant to prove the feasibility of the signal transport to the newly created readout pads on the backside of the chips allowing for four side buttable devices without the presently used cantilever for wire bonding. The read-out chips with ICVs will be interconnected to thin pixel sensors, 75 $\mu$m and 150 $\mu$m thick, with the Solid Liquid Interdiffusion (SLID) technology, which is an alternative to the standard solder bump-bonding.