Architectural considerations in the design of a superconducting quantum annealing processor

Abstract: We have developed a quantum annealing processor, based on an array of tunably coupled rf-SQUID flux qubits, fabricated in a superconducting integrated circuit process [1]. Implementing this type of processor at a scale of 512 qubits and 1472 programmable inter-qubit couplers and operating at ~ 20 mK has required attention to a number of considerations that one may ignore at the smaller scale of a few dozen or so devices. Here we discuss some of these considerations, and the delicate balance necessary for the construction of a practical processor that respects the demanding physical requirements imposed by a quantum algorithm. In particular we will review some of the design trade-offs at play in the floor-planning of the physical layout, driven by the desire to have an algorithmically useful set of inter-qubit couplers, and the simultaneous need to embed programmable control circuitry into the processor fabric. In this context we have developed a new ultra-low power embedded superconducting digital-to-analog flux converters (DACs) used to program the processor with zero static power dissipation, optimized to achieve maximum flux storage density per unit area. The 512 single-stage, 3520 two-stage, and 512 three-stage flux-DACs are controlled with an XYZ addressing scheme requiring 56 wires. Our estimate of on-chip dissipated energy for worst-case reprogramming of the whole processor is ~ 65 fJ. Several chips based on this architecture have been fabricated and operated successfully at our facility, as well as two outside facilities (see for example [2]).

• The paper demonstrates the design of a superconducting quantum annealing processor featuring 512 qubits and 1472 couplers using RF-SQUID technology.
• The authors detail the integration of superconducting DACs and innovative XYZ addressing schemes to achieve precise control with zero static power dissipation.
• The study validates energy efficiency with an estimated 65 fJ worst-case reprogramming dissipation and improved thermalization delays, supporting scalable quantum computing.

Architectural Considerations in the Design of a Superconducting Quantum Annealing Processor

The paper discusses the complex considerations involved in designing a quantum annealing processor using superconducting flux qubits. Developed by D-Wave Systems, this processor represents an evolution in quantum computing architecture, capable of operating with a configuration of 512 qubits and 1472 inter-qubit couplers. This configuration is achieved using RF-SQUID (Radio Frequency Superconducting Quantum Interference Device) technology, leveraging superconducting integrated circuits.

Key Architectural Considerations

The design of a superconducting quantum annealing processor requires meticulous planning due to the physical constraints and requirements of quantum algorithms. There are several design trade-offs and considerations, including floor planning and physical layout, which must ensure a practical processor environment while achieving algorithmically useful inter-qubit connections.

1. Superconducting Integration: The focus on superconducting qubits is notable due to compatibility with existing single-flux-quanta (SFQ) based technologies. This approach facilitates precise qubit control and high-fidelity readout, which are essential for scalable quantum computing systems.
2. Scale and Control: At the scale of hundreds of qubits, specific architectural solutions become necessary. For instance, the implementation involves embedded superconducting digital-to-analog converters (DACs) that enable programming with zero static power dissipation, incorporating innovative XYZ addressing schemes to optimize the balance between control and space.
3. Energy Efficiency: The processor design forefronts energy efficiency, illustrated by an estimated energy dissipation of approximately 65 fJ during worst-case reprogramming scenarios. This low dissipation is crucial for maintaining the low operational temperatures (~20 mK) necessary for quantum computation.

Practical Considerations and Implications

The architecture described has been practically validated across several test chips, showing successful operation under laboratory conditions. A key goal of this processor architecture is to further the D-Wave series, which has evolved through successive generations, including the D-Wave One and Two systems. These processors are subjected to practical constraints like heat dissipation and the need for fast operational readiness, seen in the significant reduction of thermalization delay from one second to ten milliseconds between generations.

The involvement with PACs (Programmable Area Controllers) and XYZ addressing allows a compact control scheme necessitated by increased qubit density. Efficient control topology and DAC design maximize magnetic flux density, which, in turn, enhances qubit interaction quality essential for solving complex optimization problems.

Future Developments

Looking forward, the architectural considerations and innovations lead to several potential future paths in quantum computing. Decreasing the footprint of control circuitry, possibly through advances in material sciences and chip layering techniques, can further enhance qubit densities. This progress would facilitate embedding more complex graph topologies, satisfying higher-order computational problems with larger quantum graphs.

Moreover, the successful implementation of the XYZ addressing and energy-efficient DACs can serve as a blueprint for future superconducting quantum annealing processors, potentially enabling the delivery of faster and more energy-efficient quantum computation capabilities across a broader range of applications.

In conclusion, the research highlights a significant step in scaling quantum annealers with considerations bridging theoretical and practical engineering, propelling the field towards commercially viable quantum systems. It opens up the potential for adopting such architectures in both research and industrial applications, where solving large-scale combinatorial optimization problems is critical.