Gate-tunable Memristive Phenonmena Mediated by Grain Boundaries in Single Layer MoS2

Abstract: Continued progress in high speed computing depends on breakthroughs in both materials synthesis and device architectures. The performance of logic and memory can be enhanced significantly by introducing a memristor, a two terminal device with internal resistance that depends on the history of the external bias voltage. State of the art memristors, based on metal insulator metal (MIM) structures with insulating oxides, such as TiO2, are limited by a lack of control over the filament formation and external control of the switching voltage. Here, we report a class of memristors based on grain boundaries (GBs) in single-layer MoS2 devices. Specifically, the resistance of GBs emerging from contacts can be easily and repeatedly modulated, with switching ratios up to 1000 and a dynamic negative differential resistance (NDR). Furthermore, the atomically thin nature of MoS2 enables tuning of the set voltage by a third gate terminal in a field-effect geometry, which provides new functionality that is not observed in other known memristive devices.