Topological and subsystem codes on low-degree graphs with flag qubits

Abstract: In this work we introduce two code families, which we call the heavy hexagon code and heavy square code. Both code families are implemented by assigning physical data and ancilla qubits to both vertices and edges of low degree graphs. Such a layout is particularly suitable for superconducting qubit architectures to minimize frequency collisions and crosstalk. In some cases, frequency collisions can be reduced by several orders of magnitude. The heavy hexagon code is a hybrid surface/Bacon-Shor code mapped onto a (heavy) hexagonal lattice whereas the heavy square code is the surface code mapped onto a (heavy) square lattice. In both cases, the lattice includes all the ancilla qubits required for fault-tolerant error-correction. Naively, the limited qubit connectivity might be thought to limit the error-correcting capability of the code to less than its full distance. Therefore, essential to our construction is the use of flag qubits. We modify minimum weight perfect matching decoding to efficiently and scalably incorporate information from measurements of the flag qubits and correct up to the full code distance while respecting the limited connectivity. Simulations show that high threshold values for both codes can be obtained using our decoding protocol. Further, our decoding scheme can be adapted to other topological code families.

• The paper introduces novel heavy hexagon and heavy square quantum error codes designed for low-degree graphs and leveraging flag qubits to enhance fault tolerance on superconducting hardware.
• These codes significantly reduce hardware constraints for superconducting qubits by minimizing required frequencies while maintaining competitive error correction thresholds compared to standard surface codes.
• Flag qubits and a specialized decoding protocol are crucial, allowing the codes to correct errors up to their theoretical maximum distance, mitigating issues caused by single faults on low-degree graphs.

Overview of Topological and Subsystem Codes on Low-Degree Graphs with Flag Qubits

This paper investigates novel approaches to implement quantum error-correcting codes (QECCs) on superconducting qubit architectures by exploiting low-degree graphs with the strategic deployment of flag qubits. The proposed work introduces two notable code families: the heavy hexagon code and the heavy square code, each offering unique structural and operational advantages in minimizing frequency collisions and enhancing fault tolerance in quantum computing systems.

The heavy hexagon code is defined as a hybrid surface/Bacon-Shor code that leverages a hexagonal lattice configuration. This approach allows for a reduced qubit degree by incorporating both vertices and edges into the lattice structure, optimizing it particularly for superconducting qubit architectures. The heavy hexagon code comprises a mix of high-weight and low-weight gauge generators, enabling efficient error correction and stabilizer measurements. The heavy square code, on the other hand, utilizes a square lattice and represents a variant of the rotated surface code, further refined with the inclusion of flag qubits to decrease qubit connectivity.

Flag qubits play a pivotal role in these codes by mitigating the consequences of single faults leading to weight-two errors, which would otherwise compromise the effective code distance. The paper delineates a decoding protocol that integrally utilizes flag qubit measurement outcomes, ensuring that the codes operate to their theoretical maximum distance. This is particularly critical as it allows the correction of errors arising from a number of faults up to half the code distance, a significant improvement over conventional methods that disregard flag information.

The proposed code architectures display several practical benefits in the domain of superconducting qubits. Notably, the heavy hexagon and heavy square codes decrease the number of distinct frequencies needed, thereby reducing the likelihood of frequency collisions that pose constraints in quantum circuit design. This frequency minimization is achieved without sacrificing error correction efficacy, as demonstrated through simulations showing competitive threshold values compared to standard surface codes.

Moreover, the research has broader implications and potential applications beyond superconducting architectures. The flexibility and reduced qubit connectivity of these codes offer prospective advantages for various quantum computing platforms where high qubit connectivity imposes fabrication challenges. The paper's insights into low-degree graph configurations and fault-tolerant quantum computing establish a foundation for future exploration into topological QECCs with efficient hardware performance.

In conclusion, the paper significantly contributes to the field by not only presenting scalable and practical quantum error-correcting codes suitable for near-term quantum devices but also by proposing a decoding scheme that fully exploits the ancillary information afforded by flag qubits. This work directs future research towards optimizing quantum architectures, focusing on minimizing noise and error rates associated with qubit interactions on physical hardware.