Experimental Characterization of Fault-Tolerant Circuits in Small-Scale Quantum Processors

Abstract: Experiments conducted on open-access cloud-based IBM Quantum devices are presented for characterizing their fault tolerance using $[4,2,2]$-encoded gate sequences. Up to 100 logical gates are activated in the IBMQ Bogota and IBMQ Santiago devices and we found that a $[4,2,2]$ code's logical gate set may be deemed fault-tolerant for gate sequences larger than 10 gates. However, certain circuits did not satisfy the fault tolerance criterion. In some cases, the encoded-gate sequences show a high error rate that is lower bounded at $\approx 0.1$, whereby the error inherent in these circuits cannot be mitigated by classical post-selection. A comparison of the experimental results to a simple error model reveals that the dominant gate errors cannot be readily represented by the popular Pauli error model. Finally, it is most accurate to assess the fault tolerance criterion when the circuits tested are restricted to those that give rise to an output state with a low dimension.