Efficient Fault Detection Architecture of Bit-Parallel Multiplier in Polynomial Basis of GF(2m) Using BCH Code

Abstract: The finite field multiplier is mainly used in many of today's state of the art digital systems and its hardware implementation for bit parallel operation may require millions of logic gates. Natural causes or soft errors in digital design could cause some of these gates to malfunction in the field, which could cause the multiplier to produce incorrect outputs. To ensure that they are not susceptible to error, it is crucial to use a finite field multiplier implementation that is effective and has a high fault detection capability. In this paper, we propose a novel fault detection scheme for a recent bit-parallel polynomial basis multiplier over GF(2m), where the proposed method aims at obtaining high fault detection performance for finite field multipliers and meanwhile maintain low-complexity implementation which is favored in resource constrained applications such as smart cards. The proposed method is based on BCH error correction codes, with an area-delay efficient architecture. The experimental results show that for 45-bit multiplier with 5-bit errors the proposed error detection and correction architecture results in 37% and %49 reduction in critical path delay with compared to the existing method in [18]. Moreover, the area overhead for 45-bit multiplier with 5 errors is within 80% which is significantly lower than the best existing BCH based fault detection method in finite field multiplier [18].