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Large-Area Spatially Ordered Mesa Top Single Quantum Dots: Suitable Single Photon Emitters for On-Chip Integrated Quantum Information Processing Platforms

Published 23 Dec 2023 in quant-ph and physics.optics | (2312.15132v3)

Abstract: Realization of the long sought on-chip scalable photonic quantum information processing networks has been thwarted by the absence of spatially-ordered and scalable on-demand single photon emitters with emission figures-of-merit exceeding the required thresholds across large numbers. The positioning must meet the required degree of accuracy that enables fabricating their interconnection to create the desired functional network. Here we report on the realization of large-area spatially-ordered arrays of mesa-top single quantum dots (MTSQDs) that are demonstrated [1] to be on-demand single photon emitters with characteristics that meet the requirements for implementing quantum photonic circuits/platforms aimed at quantum key distribution, linear optical quantum computing, simulations of quantum many-body problems, and metrology/sensing. The reported GaAs/InGaAs/GaAs MTSQD arrays, grown via SESRE (substrate-encoded size-reducing epitaxy) are in multiple arrays of up to 100x100 with 5um pitch, across a centimeter radius area. We show illustrative large-area images of the emission intensity (brightness) and color-coded wavelength distribution exhibiting ~3.35nm standard deviation. Scanning transmission electron microscopy shows a remarkable control on the QD location to within ~3nm accuracy laterally and ~1nm vertically. The primary remaining challenge is the control on the uniformity of the currently wet-chemically etched as-patterned nanomesa lateral size across the substrate, a surmountable technical issue. Thus, SESRE offers the most promising approach to realizing on-chip scalable spatially-ordered arrays of on-demand bright single quantum emitters meeting the figures-of-merit required for on-chip fully integrated quantum photonic circuit platforms-monolithic (such as based upon AlGaAs on insulator) or hybrid that leverage the silicon-on-insulator (SOI) photonic integrated circuit (PIC).

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