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BreakHammer: Enhancing RowHammer Mitigations by Carefully Throttling Suspect Threads

Published 20 Apr 2024 in cs.CR and cs.AR | (2404.13477v2)

Abstract: RowHammer is a major read disturbance mechanism in DRAM where repeatedly accessing (hammering) a row of DRAM cells (DRAM row) induces bitflips in other physically nearby DRAM rows. RowHammer solutions perform preventive actions (e.g., refresh neighbor rows of the hammered row) that mitigate such bitflips to preserve memory isolation, a fundamental building block of security and privacy in modern computing systems. However, preventive actions induce non-negligible memory request latency and system performance overheads as they interfere with memory requests. As shrinking technology node size over DRAM chip generations exacerbates RowHammer, the overheads of RowHammer solutions become prohibitively expensive. As a result, a malicious program can effectively hog the memory system and deny service to benign applications by causing many RowHammer-preventive actions. In this work, we tackle the performance overheads of RowHammer solutions by tracking and throttling the generators of memory accesses that trigger RowHammer solutions. To this end, we propose BreakHammer. BreakHammer 1) observes the time-consuming RowHammer-preventive actions of existing RowHammer mitigation mechanisms, 2) identifies hardware threads that trigger many of these actions, and 3) reduces the memory bandwidth usage of each identified thread. As such, BreakHammer significantly reduces the number of RowHammer-preventive actions performed, thereby improving 1) system performance and DRAM energy, and 2) reducing the maximum slowdown induced on a benign application, with near-zero area overhead. Our extensive evaluations demonstrate that BreakHammer effectively reduces the negative performance, energy, and fairness effects of eight RowHammer mitigation mechanisms. To foster further research we open-source our BreakHammer implementation and scripts at https://github.com/CMU-SAFARI/BreakHammer.

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References (207)
  1. Robert H. Dennard. Field-Effect Transistor Memory, 1968.
  2. Exploiting Hardware Vulnerabilities to Attack Embedded System Devices: A Survey of Potent Microarchitectural Attacks. Electronics, 2017.
  3. Attacking Deterministic Signature Schemes using Fault Attacks. In EuroS&P, 2018.
  4. Throwhammer: Rowhammer Attacks Over the Network and Defenses. In USENIX ATC, 2018.
  5. OpenSSL Bellcore’s Protection Helps Fault Attack. In DSD, 2018.
  6. Software-Only Reverse Engineering of Physical DRAM Mappings for Rowhammer Attacks. In IVSW, 2018.
  7. Triggering Rowhammer Hardware Faults on ARM: A Revisit. In ASHES, 2018.
  8. Advanced Fault Attacks in Software: Exploiting the Rowhammer Bug. In Fault Tolerant Architectures for Cryptography and Hardware Security. 2018.
  9. Exploiting the DRAM Rowhammer Bug to Gain Kernel Privileges. http://googleprojectzero.blogspot.com.tr/2015/03/exploiting-dram-rowhammer-bug-to-gain.html, 2015.
  10. Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors. In ISCA, 2014.
  11. SAFARI Research Group. RowHammer — GitHub Repository. https://github.com/CMU-SAFARI/rowhammer, 2014.
  12. Exploiting the DRAM Rowhammer Bug to Gain Kernel Privileges. Black Hat, 2015.
  13. Drammer: Deterministic Rowhammer Attacks on Mobile Platforms. In CCS, 2016.
  14. Rowhammer.js: A Remote Software-Induced Fault Attack in Javascript. arXiv:1507.06955 [cs.CR], 2016.
  15. Flip Feng Shui: Hammering a Needle in the Software Stack. In USENIX Security, 2016.
  16. DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks. In USENIX Security, 2016.
  17. One Bit Flips, One Cloud Flops: Cross-VM Row Hammer Attacks and Privilege Escalation. In USENIX Security, 2016.
  18. Dedup Est Machina: Memory Deduplication as An Advanced Exploitation Vector. In S&P, 2016.
  19. Curious Case of Rowhammer: Flipping Secret Exponent Bits Using Timing Analysis. In CHES, 2016.
  20. Invited: Who is the Major Threat to Tomorrow’s Security? You, the Hardware Designer. In DAC, 2016.
  21. A New Approach for RowHammer Attacks. In HOST, 2016.
  22. Can’t Touch This: Software-Only Mitigation Against Rowhammer Attacks Targeting Kernel Memory. In USENIX Security, 2017.
  23. SGX-Bomb: Locking Down the Processor via Rowhammer Attack. In SOSP, 2017.
  24. When Good Protections Go Bad: Exploiting Anti-DoS Measures to Accelerate Rowhammer Attacks. In HOST, 2017.
  25. Onur Mutlu. The RowHammer Problem and Other Issues We May Face as Memory Becomes Denser. In DATE, 2017.
  26. Defeating Software Mitigations Against Rowhammer: A Surgical Precision Hammer. In RAID, 2018.
  27. Another Flip in the Wall of Rowhammer Defenses. In S&P, 2018.
  28. Nethammer: Inducing Rowhammer Faults Through Network Requests. arXiv:1805.04956 [cs.CR], 2018.
  29. GuardION: Practical Mitigation of DMA-Based Rowhammer Attacks on ARM. In DIMVA, 2018.
  30. Grand Pwning Unit: Accelerating Microarchitectural Attacks with the GPU. In S&P, 2018.
  31. Exploiting Correcting Codes: On the Effectiveness of ECC Memory Against Rowhammer Attacks. In S&P, 2019.
  32. Pinpoint Rowhammer: Suppressing Unwanted Bit Flips on Rowhammer Attacks. In ASIACCS, 2019.
  33. RowHammer: A Retrospective. TCAD, 2019.
  34. Terminal Brain Damage: Exposing the Graceless Degradation in Deep Neural Networks Under Hardware Fault Attacks. In USENIX Security, 2019.
  35. RAMBleed: Reading Bits in Memory Without Accessing Them. In S&P, 2020.
  36. TRRespass: Exploiting the Many Sides of Target Row Refresh. In S&P, 2020.
  37. Are We Susceptible to Rowhammer? An End-to-End Methodology for Cloud Providers. In S&P, 2020.
  38. JackHammer: Efficient Rowhammer on Heterogeneous FPGA–CPU Platforms. arXiv:1912.11523 [cs.CR], 2020.
  39. PThammer: Cross-User-Kernel-Boundary Rowhammer through Implicit Accesses. In MICRO, 2020.
  40. Deephammer: Depleting the Intelligence of Deep Neural Networks Through Targeted Chain of Bit Flips. In USENIX Security, 2020.
  41. SMASH: Synchronized Many-Sided Rowhammer Attacks from JavaScript. In USENIX Security, 2021.
  42. Uncovering in-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications. In MICRO, 2021.
  43. Blacksmith: Scalable Rowhammering in the Frequency Domain. In S&P, 2022.
  44. Toward Realistic Backdoor Injection Attacks on DNNs using RowHammer. arXiv:2110.07683, 2022.
  45. Half-Double: Hammering From the Next Row Over. In USENIX Security, 2022.
  46. SpyHammer: Using RowHammer to Remotely Spy on Temperature. arXiv:2210.04084, 2022.
  47. Implicit Hammer: Cross-Privilege-Boundary Rowhammer through Implicit Accesses. IEEE TDSC, 2022.
  48. Generating Robust DNN with Resistance to Bit-Flip based Adversarial Weight Attack. IEEE TC, 2022.
  49. HammerScope: Observing DRAM Power Consumption Using Rowhammer. In CCS, 2022.
  50. TrojViT: Trojan Insertion in Vision Transformers. arXiv:2208.13049, 2022.
  51. When Frodo Flips: End-to-End Key Recovery on FrodoKEM via Rowhammer. CCS, 2022.
  52. SpecHammer: Combining Spectre and Rowhammer for New Speculative Attacks. In S&P, 2022.
  53. DeepSteal: Advanced Model Extractions Leveraging Efficient Weight Stealing in Memories. In S&P, 2022.
  54. Statistical Distributions of Row-Hammering Induced Failures in DDR3 Components. Microelectronics Reliability, 2016.
  55. Experiments and Root Cause Analysis for Active-Precharge Hammering Fault in DDR3 SDRAM under 3xnm Technology. Microelectronics Reliability, 2016.
  56. Active Precharge Hammering to Monitor Displacement Damage Using High-Energy Protons in 3x-nm SDRAM. TNS, 2017.
  57. Overcoming the Reliability Limitation in the Ultimately Scaled DRAM using Silicon Migration Technique by Hydrogen Annealing. In IEDM, 2017.
  58. Study of TID Effects on One Row Hammering using Gamma in DDR4 SDRAMs. In IRPS, 2018.
  59. Trap-Assisted DRAM Row Hammer Effect. EDL, 2019.
  60. On DRAM RowHammer and the Physics on Insecurity. IEEE TED, 2021.
  61. Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques. In ISCA, 2020.
  62. A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses. In MICRO, 2021.
  63. Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices. In DSN, 2022.
  64. Mohammad Nasim Imtiaz Khan and Swaroop Ghosh. Analysis of Row Hammer Attack on STTRAM. In ICCD, 2018.
  65. Rowhammer for Spin Torque based Memory: Problem or not? In INTERMAG, 2018.
  66. Write Disturb Analyses on Half-Selected Cells of Cross-Point RRAM Arrays. In IRPS, 2014.
  67. Write Disturb in Ferroelectric FETs and Its Implication for 1T-FeFET AND Memory Arrays. IEEE EDL, 2018.
  68. On the Reliability of FeFET On-Chip Memory. TC, 2022.
  69. Fundamentally Understanding and Solving RowHammer. In ASP-DAC, 2023.
  70. Cyber Security in Industrial Control Systems (ICS): A Survey of RowHammer Vulnerability. Applied Computer Science, 2022.
  71. Jolt: Recovering TLS Signing Keys via Rowhammer Faults. Cryptology ePrint Archive, 2022.
  72. Research and Implementation of Rowhammer Attack Method based on Domestic NeoKylin Operating System. In ICFTIC, 2022.
  73. Sam Lefforge. Reverse Engineering Post-Quantum Cryptography Schemes to Find Rowhammer Exploits. Master’s thesis, University of Arkansas, 2023.
  74. Michael J Fahr. The Effects of Side-Channel Attacks on Post-Quantum Cryptography: Influencing FrodoKEM Key Generation Using the Rowhammer Exploit. PhD thesis, University of Arkansas, 2022.
  75. Work-in-Progress: DRAM-MaUT: DRAM Address Mapping Unveiling Tool for ARM Devices. In CASES, 2022.
  76. On the Feasibility of Training-time Trojan Attacks through Hardware-based Faults in Memory. In HOST, 2022.
  77. CyberRadar: A PUF-based Detecting and Mapping Framework for Physical Devices. arXiv:2201.07597, 2022.
  78. Efficient Targeted Bit-Flip Attack Against the Local Binary Pattern Network. In HOST, 2022.
  79. NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. In DATE, 2022.
  80. Socially-Aware Collaborative Defense System against Bit-Flip Attack in Social Internet of Things and Its Online Assignment Optimization. In ICCCN, 2022.
  81. Signature Correction Attack on Dilithium Signature Scheme. In Euro S&P, 2022.
  82. RowPress: Amplifying Read Disturbance in Modern DRAM Chips. In Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023.
  83. BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows. In HPCA, 2021.
  84. Graphene: Strong yet Lightweight Row Hammer Protection. In MICRO, 2020.
  85. HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips. In MICRO, 2022.
  86. Arthur De Graauw. Ancient Port Structures. Parallels between the Ancient and the Modern. Méditerranée. Revue géographique des pays méditerranéens/Journal of Mediterranean geography, 2022.
  87. TWiCe: Preventing Row-Hammering by Exploiting Time Window Counters. In ISCA, 2019.
  88. AQUA: Scalable Rowhammer Mitigation by Quarantining Aggressor Rows at Runtime. In MICRO, 2022.
  89. Hydra: Enabling Low-Overhead Mitigation of Row-Hammer at Ultra-Low Thresholds via Hybrid Tracking. In ISCA, 2022.
  90. REGA: Scalable Rowhammer Mitigation with Refresh-Generating Activations. In S&P, 2023.
  91. Panopticon: A Complete In-DRAM Rowhammer Mitigation. In DRAMSec, 2021.
  92. Method and Circuit for Protecting a DRAM Memory Device from the Row Hammer Effect. US Patent: 10,885,966, 2021.
  93. Security Analysis of the Silver Bullet Technique for RowHammer Prevention. arXiv:2106.07084, 2021.
  94. CACTI: An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model. https://www.hpl.hp.com/research/cacti/, 2017.
  95. Synopsys, Inc. Synopsys Design Compiler. https://www.synopsys.com/support/training/rtl-synthesis/design-compiler-rtl-synthesis.html.
  96. JEDEC. JESD79-4C: DDR4 SDRAM Standard, 2020.
  97. JEDEC. JESD79-5: DDR5 SDRAM Standard, 2020.
  98. An Investigation into Crosstalk Noise in DRAM Structures. In MTDT, 2002.
  99. Active-Precharge Hammering on a Row-Induced Failure in DDR3 SDRAMs Under 3x nm Technology. In IIRW, 2014.
  100. Suppression of RowHammer Effect by Doping Profile Modification in Saddle-Fin Array Devices for Sub-30-nm DRAM Technology. TDMR, 2016.
  101. Scanning Spreading Resistance Microscopy for Doping Profile in Saddle-Fin Devices. IEEE Transactions on Nanotechnology, 2017.
  102. Study of Proton Radiation Effect to Row Hammer Fault in DDR4 SDRAMs. Microelectronics Reliability, 2018.
  103. Row Hammering Mitigation Using Metal Nanowire in Saddle Fin DRAM. IEEE TED, 2019.
  104. Quantifying RowHammer Vulnerability for DRAM Security. In DAC, 2021.
  105. WhistleBlower: A System-level Empirical Study on RowHammer. IEEE Transactions on Computers, 2023.
  106. Estimation of the Trap Energy Characteristics of Row Hammer-Affected Cells in Gamma-Irradiated DDR4 DRAM. IEEE Transactions on Nuclear Science, 2022.
  107. Onur Mutlu. RowHammer. https://people.inf.ethz.ch/omutlu/pub/onur-Rowhammer-TopPicksinHardwareEmbeddedSecurity-November-8-2018.pdf, 2018.
  108. An Experimental Analysis of RowHammer in HBM2 DRAM Chips. In DSN Disrupt, 2023.
  109. DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips. TCAD, 2023.
  110. Double-sided Row Hammer Effect in Sub-20 nm DRAM: Physical Mechanism, Key Features and Mitigation. In IRPS, 2023.
  111. Blaster: Characterizing the blast radius of rowhammer. In 3rd Workshop on DRAM Security (DRAMSec) co-located with ISCA 2023. ETH Zurich, 2023.
  112. Apple Inc. About the Security Content of Mac EFI Security Update 2015-001. https://support.apple.com/en-us/HT204934, 2015.
  113. Hewlett-Packard Enterprise. HP Moonshot Component Pack Version 2015.05.0, 2015.
  114. Lenovo Group Ltd. Row Hammer Privilege Escalation, 2015.
  115. Throttling Support for Row-Hammer Counters, 2016.
  116. Architectural Support for Mitigating Row Hammering in DRAM Memories. CAL, 2014.
  117. Barbara Aichinger. DDR Memory Errors Caused by Row Hammer. In HPEC, 2015.
  118. ANVIL: Software-Based Protection Against Next-Generation Rowhammer Attacks. In ASPLOS, 2016.
  119. K. Bains et al. Row Hammer Refresh Command. US Patents: 9,117,544 9,236,110 10,210,925, 2015.
  120. Row Hammer Refresh Command, 2015.
  121. Distributed Row Hammer Tracking, 2016.
  122. Row Hammer Monitoring Based on Stored Row Hammer Threshold Value. US Patent: 10,083,737, 2016.
  123. DRAM row-hammer attack reduction using dummy cells. In NORCAS, 2016.
  124. Making DRAM Stronger Against Row Hammering. In DAC, 2017.
  125. Mitigating Wordline Crosstalk Using Adaptive Trees of Counters. In ISCA, 2018.
  126. MASCAT: Stopping Microarchitectural Attacks Before Execution. IACR Cryptology, 2016.
  127. MRLoc: Mitigating Row-Hammering Based on Memory Locality. In DAC, 2019.
  128. CAT-TWO: Counter-Based Adaptive Tree, Time Window Optimized for DRAM Row-Hammer Prevention. IEEE Access, 2020.
  129. Randomized Row-Swap: Mitigating Row Hammer by Breaking Spatial Correlation Between Aggressor and Victim Rows. In ASPLOS, 2022.
  130. ZebRAM: Comprehensive and Compatible Software Protection Against Rowhammer Attacks. In OSDI, 2018.
  131. Rapid Detection of Rowhammer Attacks Using Dynamic Skewed Hash Tree. In HASP, 2018.
  132. CROW: A Low-Cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability. In ISCA, 2019.
  133. Mithril: Cooperative Row Hammer Protection on Commodity DRAM Leveraging Managed Refresh. In HPCA, 2022.
  134. CryoGuard: A Near Refresh-Free Robust DRAM Design for Cryogenic Computing. In ISCA, 2021.
  135. ProTRR: Principled yet Optimal In-DRAM Target Row Refresh. In S&P, 2022.
  136. SoftTRR: Protect Page Tables against Rowhammer Attacks using Software-only Target Row Refresh. In USENIX ATC, 2022.
  137. Learning to Mitigate RowHammer Attacks. In DATE, 2022.
  138. CSI: Rowhammer–Cryptographic Security and Integrity against Rowhammer (to appear). In S&P, 2023.
  139. Efficient Protection Mechanism for CPU Cache Flush Instruction Based Attacks. IEICE Transactions on Information and Systems, 2022.
  140. Revisiting Residue Codes for Modern Memories. In MICRO, 2022.
  141. EVAX: Towards a Practical, Pro-active & Adaptive Architecture for High Performance & Security. In MICRO, 2022.
  142. ALARM: Active LeArning of Rowhammer Mitigations. https://users.sussex.ac.uk/~mfb21/rh-draft.pdf, 2022.
  143. Machine Learning-based Rowhammer Mitigation. TCAD, 2022.
  144. A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations. arXiv:2207.13358, 2022.
  145. Leveraging EM Side-Channel Information to Detect Rowhammer Attacks. In S&P, 2020.
  146. Stop! Hammer Time: Rethinking Our Approach to Rowhammer Mitigations. In HotOS, 2021.
  147. Surround Gate Transistor With Epitaxially Grown Si Pillar and Simulation Study on Soft Error and Rowhammer Tolerance for DRAM. TED, 2021.
  148. SafeGuard: Reducing the Security Risk from Row-Hammer via Low-Cost Integrity Protection. In HPCA, 2022.
  149. The Price of Secrecy: How Hiding Internal DRAM Topologies Hurts Rowhammer Defenses. In IRPS, 2022.
  150. How to Configure Row-Sampling-Based Rowhammer Defenses. DRAMSec, 2022.
  151. MOESI-Prime: Preventing Coherence-Induced Hammering in Commodity Workloads. In ISCA, 2022.
  152. LT-PIM: An LUT-Based Processing-in-DRAM Architecture With RowHammer Self-Tracking. IEEE CAL, 2022.
  153. DSAC: Low-Cost Rowhammer Mitigation Using In-DRAM Stochastic and Approximate Counting Algorithm. arXiv:2302.03591, 2023.
  154. Copy-on-Flip: Hardening ECC Memory Against Rowhammer Attacks. In NDSS, 2023.
  155. A Review on Study of Defects of DRAM-RowHammer and Its Mitigation. Journal For Basic Sciences, 2022.
  156. Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems. In HPCA, 2023.
  157. RowHammer Reduction Using a Buried Insulator in a Buried Channel Array Transistor. IEEE Transactions on Electron Devices, 2022.
  158. SHADOW: Preventing Row Hammer in DRAM with Intra-Subarray Row Shuffling. In HPCA, 2023.
  159. A 1.1 V 16Gb DDR5 DRAM with Probabilistic-Aggressor Tracking, Refresh-Management Functionality, Per-Row Hammer Tracking, a Multi-Step Precharge, and Core-Bias Modulation for Security and Reliability Enhancement. In ISSCC, 2023.
  160. Defending SoCs with FPGAs from Rowhammer Attacks. Material Science, 2023.
  161. Criticality based Reliability from Rowhammer Attacks in Multi-User-Multi-FPGA Platform. In VLSID, 2022.
  162. Modeling Rowhammer in the gem5 Simulator. In CHES 2022-Conference on Cryptographic Hardware and Embedded Systems, 2022.
  163. Reducing the Silicon Area Overhead of Counter-Based Rowhammer Mitigations. In 18th CryptArchi Workshop, 2022.
  164. Processor security: Detecting microarchitectural attacks via count-min sketches. VLSI, 2022.
  165. Extracting the Secrets of OpenSSL with RAMBleed. Sensors, 2022.
  166. PT-Guard: Integrity-Protected Page Tables to Defend Against Breakthrough Rowhammer Attacks. In DSN, 2023.
  167. DNN-Defender: An in-DRAM Deep Neural Network Defense Mechanism for Adversarial Weight Attack. arXiv:2305.08034, 2023.
  168. Counter-Based Tree Structure for Row Hammering Mitigation in DRAM. CAL, 2017.
  169. Finding Repeated Elements. Science of Computer Programming, 1982.
  170. Compression of Pending Interest Table with Bloom Filter in Content Centric Network. In CFI, 2012.
  171. DASH: Deadline-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators. TACO, 2016.
  172. Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior. In MICRO, 2010.
  173. The Blacklisting Memory Scheduler: Achieving High Performance and Fairness at Low Cost. In ICCD, 2014.
  174. ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers. In HPCA, 2010.
  175. Fair Queuing Memory Systems. In International Symposium on Microarchitecture (MICRO-39), 2006.
  176. Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems. In ISCA, 2012.
  177. Intel Inc. 3rd Gen Intel Xeon Scalable Processors. https://www.intel.com/content/dam/www/public/us/en/documents/a1171486-icelake-productbrief-updates-r1v2.pdf.
  178. SAFARI Research Group. Ramulator V2.0. https://github.com/CMU-SAFARI/ramulator2.
  179. Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator, 2023.
  180. Scott Rixner et al. Memory Access Scheduling. In ISCA, 2000.
  181. Memory Access Scheduling. In ISCA, 2000.
  182. Controller for a Synchronous DRAM That Maximizes Throughput by Allowing Memory Requests and Commands to Be Issued Out of Order, 1997.
  183. Minimalist Open-Page: A DRAM Page-Mode Scheduling Policy for the Many-Core Era. In MICRO, 2011.
  184. A 1.1 v 16gb ddr5 dram with probabilistic-aggressor tracking, refresh-management functionality, per-row hammer tracking, a multi-step precharge, and core-bias modulation for security and reliability enhancement. In 2023 IEEE International Solid-State Circuits Conference (ISSCC), pages 1–3. IEEE, 2023.
  185. Standard Performance Evaluation Corp. SPEC CPU 2006. http://www.spec.org/cpu2006/.
  186. Standard Performance Evaluation Corp. SPEC CPU2017 Benchmarks. http://www.spec.org/cpu2017/.
  187. Transaction Processing Performance Council.
  188. MediaBench II Video: Expediting the next Generation of Video Systems Research. Microprocess. Microsyst., 2009.
  189. Benchmarking Cloud Serving Systems with YCSB. In SoCC, 2010.
  190. DRAMPower: Open-Source DRAM Power & Energy Estimation Tool. http://www.drampower.info/.
  191. Discreet-PARA: Rowhammer Defense with Low Cost and High Efficiency. In 2021 IEEE 39th International Conference on Computer Design (ICCD), 2021.
  192. Architectural Support for Mitigating Row Hammering in DRAM Memories. CAL, 2015.
  193. Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems. 2022.
  194. Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems. In USENIX Security, 2007.
  195. Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. In MICRO, 2007.
  196. Parallelism-Aware Batch Scheduling: Enhancing Both Performance and Fairness of Shared DRAM Systems. In ISCA, 2008.
  197. HAT: Heterogeneous Adaptive Throttling for On-Chip Networks. In SBAC-PAD, 2012.
  198. Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems. In ASPLOS, 2010.
  199. Prefetch-Aware Shared Resource Management for Multi-Core Systems. In ISCA, 2011.
  200. Fairness via Source Throttling: A Configurable and High Performance Fairness Substrate for Multi Core Memory Systems. In ASPLOS, 2010.
  201. Parallel Application Memory Scheduling. In MICRO, 2011.
  202. TeleHammer: A Stealthy Cross-Boundary Rowhammer Technique. arXiv:1912.03076 [cs.CR], 2019.
  203. Timothy J Dell. A White Paper on the Benefits of Chipkill-Correct ECC for PC Server Main Memory. IBM Microelectronics Division, 1997.
  204. IVEC: Off-Chip Memory Integrity Protection for Both Security and Reliability. In ISCA, 2010.
  205. SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories. In HPCA, 2018.
  206. MemGuard: A low cost and energy efficient design to support and enhance memory system reliability. In ISCA, 2014.
  207. Moinuddin Qureshi. Rethinking ECC in the Era of Row-Hammer. DRAMSec, 2021.
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