Efficient Verification of a RADAR SoC Using Formal and Simulation-Based Methods
Abstract: As the demand for Internet of Things (IoT) and Human-to-Machine Interaction (HMI) increases, modern System-on-Chips (SoCs) offering such solutions are becoming increasingly complex. This intricate design poses significant challenges for verification, particularly when time-to-market is a crucial factor for consumer electronics products. This paper presents a case study based on our work to verify a complex Radio Detection And Ranging (RADAR) based SoC that performs on-chip sensing of human motion with millimetre accuracy. We leverage both formal and simulation-based methods to complement each other and achieve verification sign-off with high confidence. While employing a requirements-driven flow approach, we demonstrate the use of different verification methods to cater to multiple requirements and highlight our know-how from the project. Additionally, we used Machine Learning (ML) based methods, specifically the Xcelium ML tool from Cadence, to improve verification throughput.
- “2.3 SOLI: A Tiny Device for a New Human Machine Interface” In 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 2021, pp. 42–44 DOI: 10.1109/ISSCC42613.2021.9365835
- “A Mutually-Exclusive Deployment of Formal and Simulation Techniques Using Proof-Core Analysis” DVCon Europe, 2017
- Serrie-Justine Chapman, Darren Galpin and Mike Bart “Requirements driven Verification methodology (for standards compliance)” DVCon Europe, 2014
- “Improving Simulation Regression Efficiency using a Machine Learning-based Method in Design Verification” DVCon Europe, 2022
- Harry Foster “2022 Wilson Research Group Functional Verification Study”, 2022
- Harry Foster “Guidelines for creating a formal verification testplan”, 2006
- Erik Seligman, Tom Schubert and M V Achutha Kiran Kumar “Formal Verification, An Essential Toolkit for Modern VLSI Design” Morgan Kaufmann Publishers, 2015
- “Advanced UVM Register Modeling” DVCon US, 2014
- Mark Litterick, Jeff Vance and Jeff Montesano “To Infinity And Beyond - Streaming Data Sequences In UVM” DVCon US, 2021
- Mark Litterick, Jeff Vance and Jeff Montesano “Be a Sequence Pro to Avoid Bad Con Sequences” DVCon US, 2019
- Aman Kumar “Pragmatic Formal Verification of Sequential Error Detection and Correction Codes (ECCs) used in Safety-Critical Design” DVCon US, 2023
- “A Semi-Formal Verification Methodology for Efficient Configuration Coverage of Highly Configurable Digital Designs” DVCon US, 2021
- Keerthikumara Devarajegowda “Model-based Generation of Assertions for Pre-silicon Verification”, 2021, pp. V\bibrangessep167 DOI: 10.26204/KLUEDO/6640
- Aman Kumar, Muhammad Ul Haque Khan and Bijitendra Mittra “Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC)” DVCon Europe, 2023
Paper Prompts
Sign up for free to create and run prompts on this paper using GPT-5.
Top Community Prompts
Collections
Sign up for free to add this paper to one or more collections.