Proteus: Enabling High-Performance Processing-Using-DRAM with Dynamic Bit-Precision, Adaptive Data Representation, and Flexible Arithmetic

Abstract: Processing-using-DRAM (PUD) is a paradigm where the analog operational properties of DRAM are used to perform bulk logic operations. While PUD promises high throughput at low energy and area cost, we uncover three limitations of existing PUD approaches that lead to significant inefficiencies: (i) static data representation, i.e., two's complement with fixed bit-precision, leading to unnecessary computation over useless (i.e., inconsequential) data; (ii) support for only throughput-oriented execution, where the high latency of individual PUD operations can only be hidden in the presence of bulk data-level parallelism; and (iii) high latency for high-precision (e.g., 32-bit) operations. To address these issues, we propose Proteus, the first hardware framework that addresses the high execution latency of bulk bitwise PUD operations by implementing a data-aware runtime engine for PUD. Proteus reduces the latency of PUD operations in three different ways: (i) Proteus dynamically reduces the bit-precision (and thus the latency and energy consumption) of PUD operations by exploiting narrow values (i.e., values with many leading zeros or ones); (ii) Proteus concurrently executes independent in-DRAM primitives belonging to a single PUD operation across multiple DRAM arrays; (iii) Proteus chooses and uses the most appropriate data representation and arithmetic algorithm implementation for a given PUD instruction transparently to the programmer.

• The paper introduces dynamic bit-precision and adaptive arithmetic, optimizing in-memory computations in DRAM.
• It leverages one-bit-per-subarray mapping to harness DRAM parallelism, reducing latency and improving resource use.
• Proteus achieves up to 17x performance and 90x energy savings, demonstrating significant benefits for data-intensive applications.

Overview of the Proteus Framework for Processing-Using-DRAM

The paper discusses Proteus, a new framework designed to enhance Processing-Using-DRAM (PuD) systems. PuD systems leverage the inherent parallelism in DRAM to execute computations in memory, rather than transferring data back and forth between the CPU and memory, which is both energy and time inefficient. The framework introduces dynamic precision, alongside adaptive arithmetic capabilities, to optimize the execution of operations in DRAM, making it significantly more efficient compared to existing computing architectures.

Core Contributions

1. Dynamic Precision and Adaptive Arithmetic: Proteus proposes a novel dynamic approach to bit-precision, meaning that the precision is tailored dynamically according to the operations' requirements. This helps in reducing unnecessary computation and power usage, which is a prevalent issue in existing PuD systems, where operations are traditionally executed using a fixed bit-width.
2. Parallelism-Aware Execution: Leveraging the internal parallelism of DRAM, Proteus introduces the one-bit-per-subarray (OBPS) data mapping, allowing multiple independent operations to be executed concurrently across different subarrays of a single DRAM bank. This results in significant latency reductions in executing bit-serial arithmetic operations.
3. Resource Efficacy: The system is designed to identify opportunities for reducing computational overhead and maximizing the throughput, leveraging mechanisms such as Narrow Values, which are common small-value data that do not require high precision. This facilitates more efficient computation in terms of both time and energy.

Experimental Evaluation

Proteus has been subject to a comprehensive experimental evaluation against several state-of-the-art computation platforms:

• Performance and Area Efficiency: In terms of performance per mm², Proteus achieves up to 17x greater efficacy compared to traditional CPU architectures and more than 10x compared to state-of-the-art SIMDRAM configurations. This demonstrates how middle ground utilization of both DRAM parallelism and dynamic precision can significantly boost efficiency and performance.
• Energy Consumption: Proteus exhibits profound energy efficiency improvements, notably consuming 90x less energy than conventional CPU operations. The focus on narrowing computation widths and leveraging in-situ processing underpins these significant savings.
• Use in Various Domains: The evaluation reveals that Proteus's dynamic precision adaptation allows for expansive utility across varied applications, including but not limited to machine learning and data analytics, which were observed to have intrinsic data bit-width variability and significant computational tasks that were effectively accelerated.

Implications and Future Directions

Proteus' design reflects a critical step toward bridging the gap between conventional data processing frameworks and innovative, energy-efficient, in-memory computation architectures. The successful employment of Proteus's framework not only paves the way for more resource-sensitive applications in data-heavy domains but also hints at potential adaptability and performance gains for more complex memory-centric computing scenarios. Future developments may focus on expanding the adaptability and support range of operations within PuD contexts, ensuring robust system compatibility across increasingly intricate computational paradigms. Moreover, further exploration of floating-point operations and extending the framework to other types of non-volatile memories could showcase additional dimensions of its applicability.