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Chip-to-chip photonic connectivity in multi-accelerator servers for ML
Published 30 Jan 2025 in cs.NI | (2501.18169v1)
Abstract: We present a rack-scale compute architecture for ML using multi-accelerator servers connected via chip-to-chip silicon photonic components. Our architecture achieves (1) multi-tenanted resource slicing without fragmentation, (2) 74% faster rack-scale collective communication, and (3) 1.7X speedup in end-to-end ML training throughput.
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