A single chip 1.024 Tb/s silicon photonics PAM4 receiver

Abstract: Energy-efficient high-bandwidth interconnects play a key role in computing systems. Advances in silicon photonic electro-optic modulators and wavelength selective components have enabled the utilization of wavelength-division-multiplexing (WDM) in integrated optical transceivers, offering a high data-rate operation while achieving enhanced energy efficiency, bandwidth density, scalability, and the reach required for data-centers. Here, we report the demonstration of a single chip optical WDM PAM4 receiver, where by co-integration of a 32-channel optical demultiplexer (O-DeMux) with autonomous wavelength tuning and locking at a near-zero power consumption and a 32-channel ultra-low power concurrent electrical detection system, a record chip energy efficiency of under 0.38 pJ/bit is measured. The implemented 32 channel monolithic WDM optical receiver chip achieves an end-to-end latency of under 100 ps and a bit-error-rate of less than 10-12 with no equalization, pre-distortion, or digital-signal-processing, while operating at 1.024 Tb/s aggregate data-rate on a single input fiber, the largest reported data-rate for a WDM PAM4 receiver chip to date. The receiver bandwidth density of more than 3.55 Tb/s/mm2 corresponds to more than an order-of-magnitude larger bandwidth density-energy efficiency product compared to the state-of-the-art optical PAM4 receivers for beyond 100Gb/s links. The chip, integrated using GlobalFoundries 45CLO CMOS-photonic process, can be used for implementation of energy-efficient high data-rate optical links for AI applications.