Cyclic Hypergraph Product Code

Abstract: Hypergraph product (HGP) codes are one of the most popular family of quantum low-density parity-check (LDPC) codes. Circuit-level simulations show that they can achieve the same logical error rate as surface codes with a reduced qubit overhead. They have been extensively optimized by importing classical techniques such as the progressive edge growth, or through random search, simulated annealing or reinforcement learning techniques. In this work, instead of ML algorithms that improve the code performance through local transformations, we impose additional global symmetries, that are hard to discover through ML, and we perform an exhaustive search. Precisely, we focus on the hypergraph product of two cyclic codes, which we call CxC codes and we study C2 codes which are the product a cyclic code with itself and CxR codes which are the product of a cyclic codes with a repetition code. We discover C2 codes and CxR codes that significantly outperform previously optimized HGP codes, achieving better parameters and a logical error rate per logical qubit that is up to three orders of magnitude better. Moreover, some C2 codes achieve simultaneously a lower logical error rate and a smaller qubit overhead than state-of-the-art LDPC codes such as the bivariate bicycle codes, at the price of a larger block length. Finally, leveraging the cyclic symmetry imposed on the codes, we design an efficient planar layout for the QCCD architecture, allowing for a trapped ion implementation of the syndrome extraction circuit in constant depth.

• The paper introduces cyclic hypergraph product codes that leverage cyclic symmetry to systematically optimize quantum LDPC codes for enhanced error correction.
• It presents two families, C2 and CxR, with C2 codes achieving logical error rates up to 2×10⁻⁸, outperforming previous ML-optimized and bicycle codes.
• The study also demonstrates a hardware-efficient, two-row planar layout for syndrome extraction, supporting scalable implementations in fault-tolerant quantum computing.

Cyclic Hypergraph Product Codes: Construction, Performance, and Implementation

Overview of Cyclic Hypergraph Product Codes

This work introduces and analyzes cyclic hypergraph product (CxC) codes, a subclass of quantum LDPC codes built as the hypergraph product of two classical cyclic codes. By leveraging cyclic symmetry, the authors substantially restrict the design space, enabling exhaustive enumerations of candidate codes and systematic optimization. The analysis covers two prominent subfamilies: C2 codes (the product of a cyclic code with itself), and CxR codes (the product of a cyclic code with a repetition code). The paper demonstrates that cyclic HGP codes generated via this approach can exhibit strong quantum error-correcting parameters and circuit-level performance, outperforming previously state-of-the-art, machine-learning optimized HGP codes.

Background and Theoretical Construction

Quantum error correction for scalable quantum computing typically employs LDPC codes, with quantum LDPCs being particularly appealing for their constant rate and growing minimum distance. Hypergraph product codes, originally proposed by Tillich and Zémor, remain a leading quantum LDPC construction by forming quantum codes from two classical codes, with flexible parameters for code length, rate, and distance. Optimizing HGP codes is a combinatorial challenge due to the size of the underlying search space.

Cyclic codes—classical linear codes defined by circulant parity-check matrices—impose strong algebraic symmetries that simplify code analysis and, crucially, reduce the space to be searched for high-performing codes. The CxC construction produces an HGP code with parameters determined by the properties of the two cyclic seeds, and, for C2 codes, by squaring a single cyclic code. CxR codes specifically pair a cyclic code with a repetition code, yielding simple stabilizer structures ideal for planar and modular layouts.

Code Families and Parameter Optimization

The authors thoroughly enumerate all cyclic classical codes with length up to 40 and check weights up to 5 (which yield quantum codes with block lengths as high as 3200 and check weights up to 10), removing codes with trivial distance or no encoded qubits. From the classical candidates, two LDPC code families are systematically constructed:

• C2 Codes: Product of a cyclic code with itself; block length $2 n_c^2$, minimum distance equal to the seed code, and code rate $(k_c/n_c)^2$.
• CxR Codes: Product of a cyclic code with a repetition code matching the distance; block length $2 n_c d_c$ and code rate $k_c/(n_c d_c)$.

Compared to earlier approaches such as random search and machine-learning methods (including simulated annealing and RL used in previous HGP code optimization), cyclic symmetry allows for an exhaustive search and discovery of codes with advantageous parameters that are otherwise difficult to find.

The parameter comparison in terms of minimum distance versus overhead shows that C2 codes match or outperform highly regarded bivariate bicycle (BB) codes and significantly exceed the performance of recent ML-optimized HGP codes, especially at higher check weights, although increased check weights may impact circuit performance.

Figure 1: Distance versus qubit overhead for C2 codes of various check weights; BB codes and ML-optimized HGP codes also shown for benchmark.

CxR codes, while suboptimal in overhead compared to C2 and BB codes, outperform prior machine-optimized codes at lower hardware complexity.

Figure 2: Distance versus qubit overhead for CxR codes compared to BB and ML-optimized HGP codes.

Circuit-Level Performance Evaluation

Realistic applicability of a code for fault-tolerance requires strong performance at the circuit level under standard noise models, not just superior code parameters. Simulations employ a realistic depolarizing noise model with significant resources, using the Stim simulator and BP+OSD decoder. Logical error rates are reported both per round and normalized by the number of encoded logical qubits to permit cross-code comparisons.

Results illustrate that C2 codes can achieve logical error rates per logical qubit up to three orders of magnitude lower than the best ML-optimized HGP codes, with examples such as the $[[882, 50, 10]]$ C2 code, which attains logical error rate per logical qubit $< 2\times 10^{-8}$, compared to $\sim 2\times 10^{-5}$ for a leading $[[625, 25, 8]]$ ML-optimized code. Notably, some C2 codes demonstrate both lower qubit overhead and lower logical error rate than leading BB codes—a regime not reached by previous constructions.

Figure 3: Circuit-level performance of C2 and CxR codes compared to BB and ML-optimized codes under circuit noise at $p=3\times10^{-3}$ and $p=10^{-3}$.

Across physical noise rates, CxC codes maintain superior performance relative to the surface code heuristic and prior HGP codes.

Figure 4: Circuit-level logical error rate curves for a selection of C2 codes and an ML-optimized HGP code.

Figure 5: Circuit-level logical error rate curves for CxR codes compared with the surface code heuristic.

Hardware Implementation and Syndrome Extraction

The cyclic code structure directly informs hardware layout efficiency. The authors propose a two-row planar layout inspired by prior works, designed for the QCCD (quantum charge-coupled device) architecture pertinent for ion trap devices. The layout aligns data and ancilla qubits via cyclic shifts in the ancilla row, enabling syndrome extraction in constant circuit depth, scalable to large code sizes. The flexible two-row arrangement also supports implementation on platforms with flying qubit capabilities.

A concrete syndrome extraction protocol is provided via an imperative algorithm operating in rounds. The cost per round scales primarily with the check weights, favoring codes with minimal polynomial weight. For architectures not supporting spatial modularity or cyclic shifts, a maximally parallel, non-modular circuit is described, applicable to monolithic hardware.

Figure 6: Packed syndrome extraction circuit for HGP codes, demonstrating maximal packing of two-qubit gates and ancilla preparation/measurement steps.

Implications, Limitations, and Outlook

The paper's results provide strong evidence that cyclic HGP codes are competitive with or exceed the performance of current leading quantum LDPC codes—including BB codes—in terms of both raw parameters and practical circuit-level error suppression, while also supporting hardware-efficient layouts. The approach underscores the value of incorporating algebraic symmetries into code design, as opposed to local, ML-based optimization, for both exhaustive search feasibility and improved code balance.

A key trade-off is that achieving simultaneous low overhead and high distance incurs increased block length compared to BB codes or surface codes, which may limit utility in NISQ-era or intermediate-scale quantum processors. High check weights may also present circuit engineering challenges, although these are mitigated by the efficient layout.

Future work should explore optimization of logical gates for these code families, as the current focus is on memory. Extending the cyclic structure to gate implementation is straightforward via existing constructions but comprehensive, hardware-aware investigation remains open. Further, as hardware matures, continued refinement of decoder implementations and layout engineering will be necessary to translate these code-theoretic advantages into experimental demonstrations.

Conclusion

This work systematically advances quantum LDPC code design by introducing cyclic hypergraph product codes and demonstrating their capacity to achieve strong error-correcting performance with practically favorable layouts. The results highlight the continued relevance of algebraic code constructions for scalable, fault-tolerant quantum computation and set the stage for further development of logical operation protocols and experimental validation across quantum platforms.