ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs

Abstract: Functional verification consumes over 50% of the IC development lifecycle, where SystemVerilog Assertions (SVAs) are indispensable for formal property verification and enhanced simulation-based debugging. However, manual SVA authoring is labor-intensive and error-prone. While LLMs show promise, their direct deployment is hindered by low functional accuracy and a severe scarcity of domain-specific data. To address these challenges, we introduce ChatSVA, an end-to-end SVA generation system built upon a multi-agent framework. At its core, the AgentBridge platform enables this multi-agent approach by systematically generating high-purity datasets, overcoming the data scarcity inherent to few-shot scenarios. Evaluated on 24 RTL designs, ChatSVA achieves 98.66% syntax and 96.12% functional pass rates, generating 139.5 SVAs per design with 82.50% function coverage. This represents a 33.3 percentage point improvement in functional correctness and an over 11x enhancement in function coverage compared to the previous state-of-the-art (SOTA). ChatSVA not only sets a new SOTA in automated SVA generation but also establishes a robust framework for solving long-chain reasoning problems in few-shot, domain-specific scenarios. An online service has been publicly released at https://www.nctieda.com/CHATDV.html.

• The paper introduces a multi-agent pipeline that decomposes SVA generation into specialized subtasks, achieving a 33.3pp improvement in functional correctness and over 11× gain in coverage.
• It leverages AgentBridge, a hybrid data synthesis platform that enforces ground-truth provenance and output verifiability to produce high-purity datasets.
• Experimental results on 24 RTL designs show significant gains, with an average of 139.5 SVAs per design and balanced detection across nearly all critical bug classes.

ChatSVA: Task-Specific LLMs for Automated SVA Generation in Hardware Verification

Background and Motivation

The functional verification phase now constitutes the majority of the integrated circuit (IC) development lifecycle, consuming over half of total project time and representing the principal bottleneck in hardware design flows. Manual development of SystemVerilog Assertions (SVAs) for Assertion-Based Verification (ABV) is both labor-intensive and error-prone, exacerbated by increasing system complexity and the shift toward domain-specific architectures.

Figure 1: IC design flow time cost distribution. Functional verification consumes 56% of development time.

Early research into automating SVA generation produced two unsatisfactory classes of approaches:

• Dynamic mining from simulation traces, which compromises formal soundness and relies on non-golden implementations;
• Traditional NLP-based static methods, which lack the semantic depth required to bridge the gap between high-level spec and functionally correct SVAs.

The emergence of LLMs made significant advances for syntactic generation, but direct, monolithic LLM-driven translation from specification to SVA remains fundamentally limited. Critically, high rates of syntactic pass do not translate into functional correctness, and coverage remains extremely poor. Efforts such as prompt engineering, RAG, or domain fine-tuning have been unable to overcome the compounding challenges of few-shot data availability and the need for compositional, structured reasoning over the multi-step property synthesis task.

Figure 2: SVA generation capabilities of LLMs: number of SVAs, syntax pass rate, function pass rate. Most models achieve high syntactic accuracy but low functional pass rates and coverage.

Methodology: Multi-Agent Long-Chain Reasoning and High-Purity Data

ChatSVA introduces a rigorously structured, multi-agent pipeline that decomposes SVA generation into compositional subtasks, mirroring expert workflows. The pipeline consists of four sequential stages, each handled by a specialized agent:

1. SpecWiz Agent: Extracts verification-relevant content and outputs a structured Verification Plan.
2. Feature Generator: Distills and modularizes verification requirements into a feature list.
3. Checkpoint Generator: Exhaustively enumerates implementation-level checkpoints anchored to features.
4. SVA Generator: Materializes checkpoints as SystemVerilog-compliant assertions for formal and simulation environments.

This decomposition induces verifiable intermediate representations, encouraging true functional alignment at every stage and mitigating functional hallucinations.

Crucially, ChatSVA's capability is fundamentally enabled by AgentBridge, a hybrid data synthesis and validation platform that generates high-purity, verified datasets for each subtask in the pipeline. AgentBridge follows three core principles:

• Directional Information Constraint: All decompositions are strictly subset relations, ensuring complete result verifiability;
• Ground-Truth Provenance: Only golden, expert-verified data is used as the dataset origin;
• Output Verifiability: Each output is subject to deterministic, task-specific verification (e.g., via formal equivalence or expert voting).

AgentBridge's closed-loop, reverse-generation and multi-agent validation suppresses false positives to virtually zero in the training set, facilitating reliable supervised fine-tuning (SFT) and domain-specific RAG.

Experimental Results

ChatSVA was evaluated on a public verification benchmark covering 24 RTL designs, using established metrics: Syntax Pass Rate (SPR), Function Pass Rate (FPR), and Function Coverage relative to known bug types. Strong baselines included GPT-4o, DeepSeek-R1, and AssertLLM (a multi-agent system representative of recent SOTA).

Main Results

• ChatSVA achieves 98.66% SPR, 96.12% FPR, and 82.50% Function Coverage, with an average of 139.5 SVAs per design.
• This constitutes a 33.3pp improvement in functional correctness and >11× gain in Function Coverage compared to SOTA (AssertLLM), which lags at 62.84% FPR and just 7.50% Function Coverage.
• Against general-purpose LLMs like GPT-4o and DeepSeek-R1, ChatSVA accelerates Function Coverage by 19.8× and 14.1×, with a corresponding >18× increase in SVA output volume.

  Figure 3: Comparative performance of ChatSVA and baselines on syntax pass, function pass, and function coverage across benchmark designs.

Ablation studies verify that performance gains derive synergistically from both:

• The explicit long-chain reasoning decomposition (S1), which alone improves FPR by +30pp even with base GPT-4o agents.
• The domain-specific, high-purity data from AgentBridge (S2), which boosts function coverage from 20.8% (workflow-only GPT-4o) to 82.5% (ChatSVA end-to-end).

Coverage and Data Quality

Comprehensive bug-type coverage analysis reveals that only ChatSVA achieves balanced, systematic detection across nearly all critical bug classes; baseline models fail both in breadth and reliability.

Figure 4: Distribution of bug detection: ChatSVA's outputs cover 15/16 bug classes, indicative of general and deep functional property capture.

AgentBridge's consensus-based reverse validation process eliminates nearly all hallucinated data: increasing the committee size from 1 to 5 agents reduces false positives in training data from 7.4% to 0.05%, with data precision exceeding 99.9%.

Figure 5: Multi-agent reverse-generation validation in AgentBridge: increasing "k" in the unanimous-consensus agent filter nearly eliminates false positives in synthesized data.

Implications and Future Directions

The demonstrated gains in functionally correct and comprehensive SVA generation point to a major advance for the adoption of LLMs in domain-specialized EDA flows, particularly where safety and soundness cannot be compromised by data poisoning or functional hallucination. ChatSVA's hybrid methodology—long-chain reasoning plus verifiable, high-fidelity data—addresses the key persistent impediments observed in prior LLM-driven design automation efforts (Xu et al., 5 Sep 2025, Hu et al., 2024, Yao et al., 2024).

Practically, ChatSVA enables a significant reduction in manual workload and lowers barriers for leveraging formal verification in large, complex SoC projects. The AgentBridge paradigm for verifiable data construction is extensible to other high-criticality, limited-data domains within hardware and potentially beyond.

From a theoretical perspective, the results highlight both the limitations of monolithic end-to-end LLM generation for compositional reasoning tasks and the necessity of pipeline-based decomposition and task-centric data engineering, especially in few-shot environments.

Future development lines include extending AgentBridge for live adaptive dataset expansion, integrating automated spec mining for further end-to-end flows, and generalizing the multi-agent, decomposition framework to additional property languages (e.g., PSL, UVM assertions) and verification regimes such as sequential equivalence or coverage-directed generation.

Conclusion

ChatSVA proposes and validates a multi-agent, long-chain reasoning approach for SVA generation, underpinned by a robust data synthesis and verification platform. The system achieves state-of-the-art functional correctness and coverage by bridging LLM reasoning limitations and data scarcity. The approach promises a scalable path forward for AI-driven formal verification in complex hardware domains and provides a reference methodology for LLM deployment in high-assurance, few-shot settings.

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