From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation

Abstract: Functional verification has become the most time-consuming phase in IC development, and Assertion-Based Verification (ABV) is key to reducing debugging time. However, existing LLM-based assertion generation methods typically pursue indiscriminate verification, aiming for maximal coverage without considering signal criticality, whereas industrial practice demands maximizing coverage with minimal verification cost. Consequently, identifying signals that have the greatest impact on design functionality and error propagation-enabling a shift from indiscriminate to targeted verification-remains a key challenge. To address this, we propose AgileAssert, a key signal-driven assertion generation framework that constructs RTL semantic graphs and identifies the top-K critical signals via a hybrid scoring and selection mechanism, followed by structure-aware RTL slicing to provide the LLM with precise targets and contextual information, thereby guiding LLMs to generate tightly constrained targeted assertions for efficient verification. Evaluated on block- and CPU-level designs, with an average 66.68% reduction in assertions, our approach outperforms three existing SOTA methods, and significantly improving coverage metrics while reducing input token consumption by 64%. In mutation testing, when our approach surpasses existing methods in error detection rate, the average number of assertions used decreases by 72.74%.

• The paper presents AgileAssert, a framework that uses LLMs to generate signal-driven assertions for efficient and targeted RTL verification.
• It employs a hybrid signal ranking method combining structural centrality, observability, and redundancy minimization to reduce assertion count by 66.68% while enhancing coverage.
• The approach leverages structure-aware RTL slicing and LLM-guided prompt construction to significantly lower token consumption and improve error detection in complex CPU-level designs.

From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation

Introduction

This paper presents AgileAssert, a novel framework for assertion-based verification (ABV) in industrial-scale register-transfer level (RTL) designs, utilizing LLMs for efficient, targeted assertion generation. Addressing the constraints of previous LLM-based approaches—most notably their indiscriminate, high-volume assertion generation and poor scalability—the work introduces a principled signal-driven methodology. AgileAssert prioritizes functionally key signals, applies structure-aware RTL slicing, and enables cost-effective, high-coverage verification even for complex CPU-level designs.

Figure 1: Efficient RTL verification through key signal-driven assertion generation.

Methodology: Signal-Driven, Structure-Aware Assertion Generation

The AgileAssert workflow is centered on three primary innovations: RTL semantic graph extraction, hybrid signal ranking, and LLM-guided, structure-aware assertion generation. The process is depicted in the system overview.

Figure 2: Workflow of AgileAssert: semantic graph construction, multi-feature signal scoring, selection, RTL slicing, and LLM-based assertion generation.

RTL Semantic Graph Construction

The extraction pipeline constructs a semantic graph from RTL code, where nodes represent signals and edges encode functional data, temporal, control, and module interaction dependencies. The approach classifies signals (state registers, control, outputs, internals), applies namespacing for hierarchical clarity, and explicitly marks combinational/sequential signals. Edges are derived from assignments (data/temporal), control structures, and module instantiations, enabling both fine- and coarse-grained behavioral dependency analysis.

Figure 3: Simplified RTL semantic graph for an I2C circuit illustrating inter-module and intra-module signal dependencies.

Hybrid Signal Ranking

Key to AgileAssert is a hybrid ranking mechanism that identifies a compact, non-redundant set of functionally critical signals most impactful for verification coverage and error propagation. The ranking integrates multiple features:

• PageRank for structural centrality,
• Observability for backward reachability,
• OutputBoost for signals connected to module outputs,
• MuxBranch for control/branching involvement.

The final signal selection employs redundancy minimization via bidirectional Jaccard similarity over reachability sets, aggressively filtering overlapping signals. Only the most impactful and complementary signals are retained for assertion generation.

Structure-Aware RTL Slicing and Prompted Assertion Generation

For each key signal, AgileAssert performs backward RTL slicing (across data, temporal, and control dependencies), producing context-minimal, functionally rich code fragments for LLM consumption. This mitigates the context-window constraints of modern LLMs, focusing attention and reducing token overhead.

Prompts for assertion generation are constructed using design overviews, hierarchical module paths, and corresponding RTL slices, maximizing context relevance for the LLM.

Figure 4: Example LLM prompt construction for signal-centric assertion generation, using c_state in the i2c_master_byte_ctrl module.

Figure 5: Example of how a signal-centric RTL slice and prompt drive targeted assertion generation for I2C's c_state signal.

Assertions are generated for each top-k signal, with correctness evaluated post-hoc. Critically, the process is robust to assertion accuracy: even with low LLM correctness, key-signal guidance allows human engineers to supply high-value manual assertions, ensuring the relevance of selected targets.

Experimental Evaluation and Results

Benchmarks and Baselines

The evaluation comprises extensive block- and CPU-level RTL designs (including I2C, SHA3, Pairing, picorv32, tinyriscv, e203) and benchmarks against recent state-of-the-art methods: AssertLLM, AssertGen, and AssertMiner. JasperGold is used for formal analysis, and GPT-5.1 for LLM-based generation.

Coverage and Efficiency Gains

AgileAssert achieves striking numerical efficiency:

• 66.68% reduction in assertion count on average
• 14.13%, 12.96%, and 11.99% improvements in branch, statement, and toggle coverage, respectively
• 21.27% increase in COI (Cone of Influence) coverage
• 64% reduction in LLM input token consumption
• In mutation testing, 72.74% fewer assertions with equal or superior error detection rates compared to baselines.

  Figure 6: Mutation testing results: stepwise key-signal addition by AgileAssert rapidly surpasses baseline error detection with substantially fewer assertions.

Assertively, in most designs, coverage plateaus after only a handful of key signals. Even in extreme-scale instances, one or two assertions on critical signals yield higher coverage than prior indiscriminate approaches. The method achieves both high-precision and cost-effective verification.

COI Efficiency Analysis

When evaluated on COI coverage versus token budget, AgileAssert strongly dominates, validating the signal-driven slicing approach in managing LLM context constraints.

Figure 7: COI coverage vs. input token cost; AgileAssert achieves target coverage with drastically fewer tokens across diverse designs.

Ablation Study

Ablative experiments dissect the hybrid scoring, showing page-ranked centrality as most influential, yet combination with observability, output boost, and branching scores (the "Full" setup) yields optimal and robust selection. Random or naive averaging results in significant COI coverage loss, validating the architectural decisions.

Figure 8: Ablation study across signal ranking variants demonstrates consistent superiority of the hybrid scoring mechanism in COI

coverage.*

Discussion and Implications

AgileAssert operationalizes a shift from brute-force assertion generation to functionally targeted, signal-driven verification. Theoretical implications include actionable metrics for signal criticality, generalized methods for source-code dependency analysis, and integration of LLMs with classical program analysis for scalable design verification.

Practically, the approach addresses the severe bottlenecks posed by RTL design scale and LLM context windows, facilitating adoption in industrial flows. The minimal-assertion, coverage-maximizing results open further avenues for iterative and interactive verification workflows, automated assertion repair, and cross-RTL/specification validation. Improvements can be explored in signal expansion handling (e.g., for structurally replicated logic), unsupervised signal category refinement, and adaptive signal selection under resource constraints.

AgileAssert directly enables more rapid design bug localization, reduced simulation cycles, and more maintainable, scalable hardware verification infrastructures. The framework is agnostic to future improvements in LLM context or reasoning, as signal ranking and slicing can leverage increased model capacity without diminishing relevance.

Conclusion

AgileAssert presents a robust, parsimonious framework for efficient RTL verification by algorithmically identifying and leveraging functionally critical signals for assertion generation. Through semantic analysis, multi-feature signal ranking, and selective RTL slicing for LLM-based assertion synthesis, it delivers superior coverage, error detection, and resource efficiency. This work substantiates the centrality of intelligent, targeted verification strategies in hardware design automation and lays groundwork for future research in AI-integrated formal verification methodologies.