Atomically Thin In₂O₃ FETs

• Atomically thin In₂O₃ FETs are semiconductor devices featuring sub-nanometer In₂O₃ channels synthesized via ALD, offering exceptional electrostatic control.
• Key fabrication techniques include low-temperature ALD channel synthesis and high-κ gate dielectric integration, enabling BEOL compatibility and 3D stacking.
• Quantum confinement effects in these devices expand the bandgap and modulate threshold voltage, driving superior performance in sub-5 nm logic applications.

Atomically thin indium oxide (In₂O₃) field-effect transistors (FETs) are an emergent category of semiconductor devices leveraging sub-nanometer to a few nanometer-thick amorphous or polycrystalline In₂O₃ channels, fabricated predominantly using atomic layer deposition (ALD). These FETs exhibit high on-state currents, steep subthreshold characteristics, and superior short-channel immunity, positioning them as promising alternatives to conventional silicon-based and two-dimensional (2D) van der Waals semiconductors for next-generation logic and memory, especially in back-end-of-line (BEOL) compatible and 3D monolithic integration architectures. This landscape encompasses experimental demonstrations of channel thicknesses down to 0.4–0.7 nm and gate lengths scaling feasibly into the sub-5 nm regime.

1. Materials Synthesis and Device Fabrication

Atomically thin In₂O₃ channels are realized using ALD, a process conferring atomic-scale thickness control and wafer-scale uniformity. Standard fabrication flows employ low thermal budget processing (≤225 °C), enabling conformal growth compatible with BEOL or sequential 3D stacking. Key elements include:

• Channel Synthesis: ALD of In₂O₃ is performed at 225 °C using trimethylindium (TMIn) and H₂O precursors, with a typical growth rate of ≈0.1 nm/cycle (Si et al., 2022, Si et al., 2020, Xu et al., 2023). Thicknesses from 0.4 nm (monolayer) to several nm are achieved by modulating cycle count, with step-edge AFM and cross-sectional TEM confirming sub-nm uniformity and conformality.
• Gate Dielectrics: HfO₂ (atomic layer deposited, 200 °C) serves as the high-κ gate oxide, with physical thicknesses down to 3 nm (equivalent oxide thickness, EOT, of 0.84–2.1 nm) (Si et al., 2022, Si et al., 2020, Lin et al., 2022). Al₂O₃ caps (<2 nm) are occasionally used for passivation and interface tuning (Si et al., 2020).
• Device Architectures: Planar, dual-gate, and gate-all-around (GAA) configurations are implemented. GAA nanoribbon In₂O₃ FETs with sub-5 nm channel thickness and widths <40 nm exhibit enhanced electrostatic control and DIBL suppression (Zhang et al., 2022).
• Contact Formation: Ni (~30–80 nm) is the preferred source/drain/gate electrode, deposited by e-beam evaporation. The In₂O₃ charge-neutrality level (CNL) alignment enables Ohmic contacts with Rc < 0.08 Ω·mm, mainly through deep Fermi level pinning above the conduction band (Si et al., 2022, Si et al., 2020).
• Channel Definition and Isolation: Electron-beam lithography followed by BCl₃/Ar ICP dry etch achieves channel lengths down to 7–8 nm and widths <200 nm (Si et al., 2022, Lin et al., 2022, Zhang et al., 2022). Wet etching with HCl is used for additional isolation.

Fabrication Table

Process Element	Parameter Range	Reference
ALD In₂O₃	0.4–3.5 nm @ 225 °C	(Si et al., 2022, Si et al., 2020, Xu et al., 2023, Lin et al., 2022)
ALD HfO₂	3–10 nm @ 200 °C	(Si et al., 2022, Si et al., 2020, Xu et al., 2023)
Channel Length	7 nm up to 1 μm	(Si et al., 2022, Lin et al., 2022, Zhang et al., 2022)
Contact Metal	Ni (30–80 nm)	(Si et al., 2022, Si et al., 2020, Zhang et al., 2022)

2. Material Properties and Quantum Confinement Effects

Atomically thin In₂O₃ films, when reduced to monolayer or few-layer thicknesses, undergo pronounced quantum confinement, modifying both the band structure and the electrostatics of the FET channel:

• Bandgap Expansion: DFT calculations and experimental measurements reveal that as thickness decreases from bulk to sub-1.5 nm, the bandgap expands from ≈1.4 eV (bulk) to ≈2.4 eV (0.7 nm), owing to quantum-well effects (Si et al., 2020, Xu et al., 2023).
• Trap Neutral Level (TNL) Shift: In₂O₃’s bulk TNL, located ∼0.4 eV above the conduction band minimum, is shifted into the bandgap for t < 1.5 nm due to the upward shift of E_C. This results in intrinsic carrier depletion at zero gate bias, enabling enhancement-mode ("normally off") operation (Si et al., 2020).
• Surface Roughness & Morphology: AFM studies establish atomically smooth (R_q ≈ 0.16 nm), amorphous or fine-grained polycrystalline ALD In₂O₃, suppressing roughness-limited scattering (Si et al., 2022, Lin et al., 2022).
• Carrier Effective Mass and DOS: Quantum confinement increases the conduction band effective mass modestly (e.g., from ≈0.17 m₀ bulk to ≈0.30 m₀ at 1 nm thickness), and the low density of states (DOS) enables a deeper Fermi level for a given carrier sheet density compared to Si, thereby enhancing injection velocity (Lin et al., 2022).

3. Electrical Performance Metrics and Scaling Behavior

Atomically thin In₂O₃ FETs display exceptional characteristics under aggressive scaling of both channel thickness and length:

• On-State Current (I_ON) and Transconductance (g_m):
  • I_ON up to 19.3 mA/μm in GAA nanoribbon devices (T_IO=3.1 nm, L_ch=40 nm, W_ch=30 nm, HfO₂=5 nm) (Zhang et al., 2022).
  • I_ON,max = 10.2 A/mm at V_GS=1 V, V_DS=1.4 V for planar devices (T_ch=2.5 nm, L_ch=7 nm) (Lin et al., 2022).
  • Record planar g_m = 4 S/mm at V_DS=1.4 V (Lin et al., 2022); g_m = 1.5 S/mm at V_DS=1 V for L_ch=50 nm, T_ch=2.5 nm, EOT=0.84 nm (Si et al., 2022).
• Subthreshold Slope (SS):
  • SS as low as 63.5 mV/dec (near theoretical limit) for T_ch=2 nm, HfO₂=5 nm (Lin et al., 2022).
  • SS = 88–130 mV/dec across T_ch=3.5–0.5 nm and EOT down to 0.84 nm (Si et al., 2022, Si et al., 2020).
• On/Off Ratio: Ion/Ioff > 10⁷ for T_ch≥0.5 nm devices; off-state limited by gate leakage in shortest channels (Si et al., 2022, Si et al., 2020).
• Threshold Voltage (V_th): Enhanced-mode V_th (+0.1 V to +4.5 V) for T_ch<1.2 nm; strong T_ch dependence due to TNL and quantum confinement (Si et al., 2020, Si et al., 2020).
• Field-Effect Mobility (μ_FE): μ_FE up to 77 cm²/V·s for T_ch=1.5 nm (Si et al., 2020); μ_FE > 20 cm²/V·s sustained below T_ch ≈1 nm (Si et al., 2022). μ_FE up to 100 cm²/V·s reported for optimal interface quality and channel configuration (Lin et al., 2022, Zhang et al., 2022).
• Contact Resistance (R_c): R_c < 0.08 Ω·mm for L_ch=8 nm, attributed to CNL pinning and high sheet carrier density (Si et al., 2022, Si et al., 2020).

Table: Electrical Metrics for Selected Atomically Thin In₂O₃ FETs

Device Type	I_ON (A/mm or mA/μm)	SS (mV/dec)	μ_FE (cm²/V·s)	R_c (Ω·mm)	Ref
Planar, 8 nm L_ch	3.1 A/mm	109–114	>20	<0.08	(Si et al., 2022)
GAA Nanoribbon, 40 nm	19.3 mA/μm	100–120	50–100	—	(Zhang et al., 2022)
Planar, 7 nm L_ch	10.2 A/mm	63.5	>100	<0.1	(Lin et al., 2022)
Planar, 40 nm L_ch	2.0 A/mm	88	39–77	0.06	(Si et al., 2020)

4. Physical Modeling, Quantum Transport, and Performance Limits

Comprehensive understanding of transport and scaling relies on analytical modeling, DFT, and ab initio quantum transport simulation:

• Charge and Current:
  • Channel sheet density:

  $n_{2D} = \frac{C_{ox}(V_{GS} - V_{th})}{q}$

  where $C_{ox} = \varepsilon_0 \varepsilon_{ox} / t_{ox}$. - Drain current (ballistic limit):

  $I_D = q n_{2D} v_e W$

  with $v_e$ the electron velocity, which can approach $10^7$ cm/s in thinnest films (Lin et al., 2022).

• Ballistic and Quasi-Ballistic Regime: Mean free path $\lambda \sim$ 8 nm (from mobility and $v_e$) means L_ch in 7–40 nm regime approaches ballistic transport (Lin et al., 2022, Xu et al., 2023).
• DFT-NEGF Simulations: For L_g=1–4 nm and t_ch=0.43 nm, simulated I_ON = 0.3–1.0 mA/μm, delay τ = 0.095–0.14 ps, and energy‐delay product EDP = $2.5\times10^{-29}–6\times10^{-32}$ J·s/μm, all surpassing ITRS high-performance and low-power targets. Comparison to monolayer MoS₂ and MoTe₂ indicates factors of 2–5 lower EDP for atomically thin In₂O₃ (Xu et al., 2023).
• Quantum Confinement Control: Tuning T_ch shifts V_th via quantum-well-induced conduction band upshift, enabling enhancement/depletion mode transition without extrinsic doping (Si et al., 2020).

5. Device Architecture, Electrostatics, and Short-Channel Effects

Device electrostatics are governed by channel thickness, gate architecture, and dielectric scaling:

• GAA Geometry: Surround-gate (GAA) architectures empirically yield the highest I_ON, best SS, and lowest DIBL due to 360° gate control, and suppress short-channel effects even at sub-40 nm L_ch (Zhang et al., 2022).
• Scaling of EOT: Down to 0.84 nm HfO₂ provides strong gate electrostatics, minimizing DIBL and maintaining SS ~110 mV/dec for L_ch ≥8 nm (Si et al., 2022, Si et al., 2020).
• Heat Dissipation: Channel widths <200 nm and pulsed I–V mitigate self-heating concerns, as demonstrated in narrow nanoribbons (Zhang et al., 2022).
• Contact Engineering: Deep CNL alignment at oxide/oxide and oxide/metal interfaces ensures low R_c, minimal Schottky barrier, and high carrier injection at high sheet densities (Si et al., 2022, Lin et al., 2022).

6. Benchmarking, Applications, and Integration Prospects

Comprehensive benchmarking demonstrates the leading figures of merit for atomically thin In₂O₃ FETs among oxide, silicon, III–V, and 2D semiconductors:

• Benchmark vs. Conventional FETs: Atomically thin In₂O₃ devices exceed or match drive currents of Si (∼1–2 A/mm), GaN (∼3–4 A/mm), InGaAs (∼2 A/mm), and monolayer TMDCs, while providing a true bandgap and superior subthreshold swing (Lin et al., 2022, Xu et al., 2023).
• BEOL Compatibility and 3D IC: Full process flow including ALD channel and gate dielectric below 225–300 °C enables monolithic stacking and integration within back-end-of-line, not achievable with traditional high-mobility materials (Si et al., 2022, Si et al., 2020, Xu et al., 2023).
• CMOS and RF Applications: High n₂D, v_e, and g_m are compatible with low-voltage digital logic (V_DS <1.5 V), high-speed (f_T/f_max >100 GHz projected), and high-frequency analog/RF front-ends (Lin et al., 2022).
• Atomic-Layer Precision and Wafer-Scale Control: Uniformity <0.1 nm variation, sub-5% thickness distribution, and conformity on 3D topologies suit large-area VLSI (Si et al., 2020, Zhang et al., 2022).

7. Fundamental and Applied Challenges, Outlook

• Threshold Voltage Engineering: Current as-grown devices may exhibit negative V_th at thicker channels; work-function engineering or gate stack adjustments are essential for robust enhancement-mode operation, especially for logic compatibility (Lin et al., 2022).
• Reliability Concerns: Long-term performance under high fields, bias stress, and irradiation is unaddressed experimentally at the atomic scale (Xu et al., 2023).
• Contact and Access Resistance Scaling: Although Rc is already low, further reductions and access geometry optimization will be needed at deep-sub-10 nm L_ch (Xu et al., 2023).
• Integration and Uniformity: Large-area uniformity, suppression of interface state density, and defect control are critical for volume manufacturing (Lin et al., 2022).
• Ultimate Scaling Limits: Ab initio simulation suggests HP operation is feasible down to L_g ≈2 nm and low-power logic down to L_g ≈3 nm, with robust energy-delay scaling and off-state leakage control, outperforming MoS₂ and MoTe₂ (Xu et al., 2023).

A plausible implication is that atomically thin In₂O₃ FETs, due to their quantum-confined electrostatics, unique CNL alignment, and ALD-enabled integration, offer a scalable oxide-semiconductor platform for sub-5 nm node logic, RF, and 3D monolithic chip technologies.

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Key References: (Si et al., 2022, Si et al., 2020, Xu et al., 2023, Lin et al., 2022, Zhang et al., 2022, Si et al., 2020)