Current-Mode Neuromodulable Silicon Neurons

• Current-mode neuromodulable silicon neurons are analog circuits that replicate adaptive spiking and bursting dynamics with tunable feedback control.
• They leverage differential-pair integrators and current-mode sigmoids to implement robust, low-power neuromorphic computation for edge processing and robotics.
• Experimental results demonstrate smooth transitions between tonic spiking and bursting, ensuring resilience to parameter variations and temperature changes.

Current-mode neuromodulable silicon neurons are analog neuromorphic circuit modules designed to emulate the adaptive and context-sensitive spiking and bursting dynamics of biological neurons by leveraging current-mode computation and tunable modulatory control of feedback loops. They enable robust computation, context-dependent switching between different modes (e.g., tonic spiking versus bursting), energy efficiency, and adaptability, making them prime candidates for real-world neuromorphic applications in edge computing and robotics (Mendolia et al., 30 Nov 2025, Ribar et al., 2018, Castaños et al., 2016).

1. Circuit Architecture and CMOS Realization

Current-mode neuromodulable silicon neurons fundamentally employ a modular subthreshold CMOS architecture consisting of differential-pair integrators (DPI) configured as low-pass filters for membrane integration, slow adaptation, and ultra-slow feedback. The high-level schematic (180 nm CMOS) includes:

• Three DPI subcircuits: Each realizes a distinct time-constant—fast ($C_f$), slow ($C_s$), and ultraslow ($C_u$). Outputs are labeled $I_f$ (membrane), $I_s$ (slow adaptation), and $I_u$ (ultraslow adaptation).
• Current-mode sigmoids: Comparator-gain blocks inject positive feedback; their gain is controlled and inactivated by adaptation currents $I_s$ and $I_u$.
• Fast positive feedback: $\mathcal S_f(\cdot)$ augments spike upstroke, slow positive feedback $\mathcal S_s(\cdot)$ enables regenerative burst mechanisms.
• Inactivation: Implemented by subtracting adaptation currents from the gain biases, ensuring both repolarization and burst containment.

ASIC implementation details include capacitance values ($C_f \approx 200\!-\!500\,\mathrm{fF}$, $C_s \approx 2\!-\!5\,\mathrm{pF}$, $C_u \approx 10\!-\!30\,\mathrm{pF}$), cell area (3800 µm²), static power (<3 nW), and per-spike energy (40–200 pJ) (Mendolia et al., 30 Nov 2025).

2. Mathematical Modeling and Feedback Dynamics

The circuit’s dynamical behavior is formalized by a set of coupled first-order differential equations:

$$\begin{aligned} \tau_f\,\frac{dI_f}{dt} &= -I_f + G_f [\mathcal S_f(I_f;I_{G_f}) + \mathcal S_s(I_s;I_{G_s}) - I_s - I_u + I_{app}] \ \tau_s\,\frac{dI_s}{dt} &= -I_s + G_s I_f \ \tau_u\,\frac{dI_u}{dt} &= -I_u + G_u I_f \end{aligned}$$

Where $G_x$ are DPI gains, $\mathcal S_x$ are current-mode sigmoid feedbacks, and inactivation is realized by time-dependent subtraction of adaptation currents from the sigmoid gain biases: $$I_{G_f}(t) = I_{G_f,0} - I_s(t), \quad I_{G_s}(t) = I_{G_s,0} - I_u(t)$$

Neuromodulation is achieved primarily by adjustment of $I_{G_s,0}$, which controls the depth of slow-loop bistability—higher values enable bursting, lower values yield tonic spiking.

This mathematical structure matches both the input-output and phase-plane properties of conductance-based models and normal-form bifurcation geometries (Mendolia et al., 30 Nov 2025, Castaños et al., 2016).

3. Analysis, Tuning, and Robustness

Analysis proceeds by exploiting time-scale separation ($\tau_f \ll \tau_s \ll \tau_u$), and steady-state response curves (“I–I curves”) reveal bistable regimes corresponding to spiking and bursting. Critical tuning parameters include:

• Capacitor ratios: $C_s/C_f$, $C_u/C_s$ set time constants across several orders of magnitude.
• DPI biases: $I_{\mathrm{th}}$, $I_\tau$ control loop gain vs. leak.
• Sigmoid thresholds and gains: $I_{\mathrm{thr}}, I_{\mathrm{lin}}, I_G$ set transition points and feedback strength.
• Current-scaling invariance: Uniform scaling of all bias currents preserves qualitative dynamics and facilitates adaptability across manufacturing spreads and operational temperatures (5–45 °C).

Experimental data show invariance of firing patterns and bistability under ×100 scaling and temperature variation, supporting robustness for large-scale deployment (Mendolia et al., 30 Nov 2025, Ribar et al., 2018).

4. Neuromodulation Mechanisms

Current-mode neuromodulation is characterized by direct modulation of the slow feedback gain bias ($I_{G_s,0}$), which emulates biological control of ionic conductances. Increasing this bias deepens the regenerative slow-loop, enabling burst generation, with ultra-slow inactivation ($I_u$) terminating bursts by gain subtraction.

Key firing characteristics and transitions are predicted by IV-curve geometry and bifurcation theory. For example, Type-I firing rates scale as $$f \approx \frac{1}{\tau_f}\ln(\frac{I_{app}-I_{leak}}{I_{th}})$$, and burst duration is logarithmically proportional to the neuromodulatory bias.

MOSFET-based implementations use subthreshold diff-pair amplifiers; bias voltages (modulatory signals) reshape the IV characteristics and bifurcation thresholds in real time (Ribar et al., 2018). NPN transistor network designs utilize normal-form geometry to guarantee singularity-protected mode transitions (Castaños et al., 2016).

5. Experimental Validation and Comparative Results

Experimental findings on the 180 nm prototype demonstrate:

• f–I curves: Tonic spike frequencies 2–50 Hz, bursts up to 20 Hz for 0.1–3 nA applied input.
• Smooth spiking↔bursting transitions: Increasing $I_{G_s}$ at fixed input yields transitions from single spikes to bursts of 3–5 spikes, with stable interburst intervals.
• Temperature robustness: Firing rates and burst durations vary smoothly with temperature (0.5–25 Hz, shortening burst size at higher temperatures), with no qualitative loss of bistability.
• Energy and area verification: Theory and SPICE simulations match measured energy/spike (41–217 pJ) and per-cell layout (~3800 µm²).
• SPICE simulations: For diff-pair MOSFET neuron, power <1 µW, dynamic adjustment of amplitude/frequency, robust I–F and bursting transitions under ±10% parameter spread (Ribar et al., 2018).

6. Performance Characteristics and Neuromorphic Applications

Current-mode neuromodulable silicon neurons demonstrate favorable metrics for integration in advanced neuromorphic systems:

Metric	CMOS DPI (180 nm) (Mendolia et al., 30 Nov 2025)	MOSFET diff-pair (Ribar et al., 2018)
Area per neuron	3800 µm²	85 µm²
Rest power	3 nW	0.77 µW
Energy per spike	40–200 pJ	— (sub-µJ per burst)
Bandwidth	200–500 Hz (spiking)	—
Modulation range	Tonic↔burst, Type I/II	Spiking↔burst, amplitude, freq

Adaptivity through neuromodulation supports use cases in central pattern generators (CPGs), context-dependent sensors, and low-power edge processing. The design’s modularity and analog feedback architecture simplify scaling, with one voltage/bias per neuron controlling excitability and firing mode. This approach directly implements conductance-geometry replicating the physiological excitability of biological neurons, and demonstrates tolerance to process and environmental variation.

7. Context Within Neuromorphic Engineering

The research trajectory from normal-form geometric organizing principles (Castaños et al., 2016) through differential-pair analog circuits (Ribar et al., 2018) to minimal subthreshold CMOS DPI implementations (Mendolia et al., 30 Nov 2025) marks the consolidation of robust, tunable, and highly modular neuromodulable neuron architectures in the silicon domain. Methodologies emphasize shaping static IV curves by parallel interconnection and gain modulation, enabling accurate control of firing patterns with input-output mappings paralleling biological mechanisms. All experimental demonstrations confirm the predicted bifurcation structures and robustness, underlining the translational integrity of this approach for large-scale, adaptive neuromorphic systems.