Flash Updating Mechanisms

• Flash updating mechanisms are techniques designed to optimize flash memory updates by harnessing asymmetric programming characteristics and reducing block erasures.
• They employ hardware-aware rewriting codes, garbage collection strategies, and system-level mappings to maximize in-place rewrites and extend device endurance.
• Energy-aware OTA protocols consolidate multiple writes into single operations, ensuring reliable updates in batteryless or energy-harvesting environments.

Flash updating mechanisms refer to system-level, coding, and management techniques designed to efficiently and reliably update data in flash memory—non-volatile storage characterized by its asymmetric program/erase characteristics. In flash memory, cells can be programmed to increase their charge state (and thus data value) incrementally, but reducing a cell's level requires erasing a large block of cells, which is slow, energy-intensive, and leads to wear. Flash updating mechanisms encompass hardware-aware algorithms, rewriting codes, garbage collection, and application-level protocols that aim to maximize in-place updates, reduce erase cycles, and ensure data persistence in the presence of power failures or fluctuating energy—especially crucial in batteryless or energy-harvesting systems.

1. Flash Memory Constraints and Motivation for Flash Updating Mechanisms

Flash memory is built from arrays of floating-gate cells, each capable of storing $q$ discrete levels. These cells are grouped into blocks; updates that reduce a cell’s charge level necessitate erasing the entire enclosing block, an operation that is fundamentally slow (hundreds of microseconds), energy-inefficient, and accelerates wear (limiting endurance to 10⁴–10⁵ cycles per block) (Yaakobi et al., 2012, Dayan et al., 2015). Consequently, flash updating mechanisms must:

• Maximize the number of user-visible writes (or rewrites) that can be performed before an erase is needed.
• Prevent and minimize write amplification—where physical writes exceed logical updates.
• Support partial and incremental firmware or data updates without incurring unnecessary erase operations.
• Guarantee atomicity and recoverability in the face of interruptions, such as power loss in harvested systems (Wei et al., 2024).

Addressing these constraints is central to the design of modern storage systems, flash translation layers (FTLs), rewriting codes, and over-the-air (OTA) update protocols.

2. Rewriting Codes for Flash Updating

A fundamental approach to flash updating is the use of rewriting codes, which exploit the asymmetric increase-only property of cell levels. An $(n, k, t)_q$ flash code stores $k$ bits in $n$ $q$-level cells, enabling up to $t$ incremental rewrites without an erase (Yaakobi et al., 2012).

Key characteristics of rewriting codes for flash updates:

• Deficiency: The minimum unused cell-level increments, defined as $\delta(C) = n(q-1) - t$, reflects code inefficiency. It is impossible to exceed $n(q-1)$ total updates per block due to the cell-level constraints (Yaakobi et al., 2012).
• Code Constructions: Advanced schemes use index-less block codes, recursive indexing, and stacked binary indexing to approach the theoretical optimum. Rewriting code constructions exist with write deficiency $O(qk\log k)$ for $q \geq \log_2 k$, nearly attaining the lower bound $\Omega(qk)$ (Yaakobi et al., 2012).
• Buffer Codes: Designed for storing sliding windows ("last-$r$") of symbols, with cyclic “shift-and-stamp” mechanisms providing $t=(q-1)(n-r)$ rewrites before erasure (Yaakobi et al., 2012).

Such codes map data updates to strictly increasing cell levels wherever possible, deferring block erasure by maximizing in-place rewrites. The trajectory code framework generalizes this to arbitrary update graphs (data-state transitions) and supports both deterministic and robust randomized approaches (Anxiao et al., 2010).

3. System-Level Update and Garbage Collection Mechanisms

Application of flash updating at the system level, such as in FTLs, involves layering logical-to-physical address mapping, out-of-place updates, and garbage collection.

• Out-of-place Updates: On each write, the FTL allocates a new physical page, stores the updated data, and marks the prior version invalid, thus avoiding immediate erasure (Dayan et al., 2015).
• Garbage Collection (GC): Background process selecting erase blocks with a high proportion of invalid pages, migrating valid data, and erasing the block for reuse.
• GC Metadata Maintenance: Two principal schemes for tracking page validity in flash-resident mapping FTLs are Lazy Gecko (RAM-resident bitmap, efficient if RAM is abundant) and Logarithmic Gecko (PVB as an LSM-tree in flash, reducing RAM footprint by >90% at the cost of modest write/read amplification) (Dayan et al., 2015).

GC Scheme	RAM Overhead	Write/Read Amplification
Lazy Gecko	$(K\cdot B)/8$ bytes	Minimal
Logarithmic Gecko	$O(P(L+2))$ bytes	$<$3% extra writes, small reads

Here $K$ = # blocks, $B$ = pages per block, $P$ = page size, $L$ = levels in LSM tree.

Critical system properties include minimizing RAM for metadata to prioritize caching, and ensuring low-overhead updates to improve both device endurance and performance (Dayan et al., 2015).

4. OTA Flash Updating and Energy-Aware Incremental Mechanisms

Batteryless, energy-harvesting IoT devices require specialized flash updating mechanisms to manage limited and intermittent power. Energy-aware incremental OTA update strategies address these challenges as follows (Wei et al., 2024):

1. Segment-Based Update Packetization: Each update packet conveys delta-changes targeting a single flash segment, minimizing extraneous flash activity and supporting precise, localized updates.
2. Deferred Flash Segment Writes: Intermediate packets (defer_flag=1) are staged in SRAM; only upon receiving the last segment packet (defer_flag=0) is the segment reconstructed in SRAM and written once, thus collapsing multiple intermediate write events into a single erase/write cycle.
3. Checkpoint-Free Update Resumption: Progress is tracked in volatile state. Upon power loss, no flash checkpoint is needed; instead, the device requests resend from the next incomplete segment, with the update distributor maintaining delivery state.

Formal energy and time models derived in (Wei et al., 2024) are:

$$E_{\text{total}} = E_{\text{comm}} + E_{\text{flash}} = E_b N_{\text{tx}} + N_{\text{seg,e}} E_e + N_{\text{seg,w}} E_w + N_{\text{seg,r}} E_r$$

$$T_{\text{total}} = T_{\text{comm}} + T_{\text{flash}}$$

Experimentally, these mechanisms reduce firmware update energy by ≈38% and update time by ≈25% as compared to naïve incremental approaches, with minimal retransmission cost upon interruptions (Wei et al., 2024).

5. Practical Trade-offs and Design Considerations

Flash updating mechanisms involve multiple trade-offs at both coding and system layers:

• Metadata Size vs. RAM Availability: Techniques such as Logarithmic Gecko are essential when RAM is scarce, despite mildly increased write/read amplification (Dayan et al., 2015).
• Code Deficiency vs. Complexity: Sophisticated code constructions (e.g., recursive indexing, trajectory codes) reduce write deficiency but may introduce decoding/encoding complexity (Yaakobi et al., 2012, Anxiao et al., 2010).
• OTA Packet Size vs. Protocol Overhead: Small update packets improve energy granularity but raise protocol overhead; large packets reduce protocol overhead at potential cost of wasted bandwidth (Wei et al., 2024).
• Checkpoint-Free vs. Checkpointing: Eliminating flash-resident checkpoints in energy-harvesting systems reduces flash wear and overhead at some retransmission cost; suitable when erase/write energy is much higher than transmission (Wei et al., 2024).

Practical mechanisms are selected based on non-volatile memory characteristics, system memory constraints, endurance requirements, and update scenario—single-cell vs. multi-cell, DRAM-cached or fully flash-resident mappings, normal or energy-harvesting environments.

6. Historical Context and Future Directions

Early flash systems relied on basic out-of-place updating with simple page mapping and eager garbage collection. The development of WOM codes, floating codes, and buffer codes laid the foundation for modern rewriting code approaches, offering order-of-magnitude improvements in both guaranteed rewrite count and endurance (Yaakobi et al., 2012, Anxiao et al., 2010).

System-level innovations, such as page-associative mapping with RAM-resident caches and advanced GC metadata strategies, have permitted high-density, large-capacity SSDs to exploit flash characteristics efficiently even with stringent hardware limitations (Dayan et al., 2015).

In energy-constrained contexts, incremental and energy-aware coalescing mechanisms for OTA updates now provide practical solutions that significantly extend device operational time and resilience in the face of unreliable energy supply (Wei et al., 2024).

Ongoing research challenges include further closing the gap between code deficiency and the information-theoretic optimum, integration with error correction and wear-leveling across physical blocks, and extending these approaches to new device classes and system architectures. Novel mechanisms leveraging device-specific features (e.g., Open-Channel SSDs, as in WLFC) may provide additional gains in reducing write amplification and metadata persistence overheads (Dong et al., 2021).