Hybrid CiM Architectures

• Hybrid CiM is a class of integrated circuits that merge analog and digital processing within memory arrays, enabling energy-efficient, precise computations.
• Partitioning strategies, such as bit-width division and precision adaptive splits, allow the system to balance low-energy analog computation with digital noise correction.
• Robust system integration incorporates digital calibration, dynamic resource allocation, and software co-design to address non-idealities and optimize performance in AI and edge applications.

Hybrid Compute-in-Memory (CiM) architectures represent a class of integrated circuits that co-locate analog and digital processing within memory arrays, partitioning workload phases or precision boundaries to optimize both energy efficiency and computational accuracy. These architectures have emerged in response to the dichotomy between purely digital CiM—providing high precision but suffering from substantial energy and area overheads—and purely analog CiM—which excels in energy and area efficiency within limited precision envelopes but is vulnerable to device non-idealities, process variation, and peripheral circuit bottlenecks. Hybrid CiM approaches, incorporating selective digital correction, split precision, dual-mode operations, or mixed-signal pipelines, are now foundational in energy-constrained AI, edge inference, time-domain neuromorphic, and robust deep learning accelerators.

1. Hybrid CiM Architectural Fundamentals

Hybrid CiM systems instantiate both analog ("ACIM") and digital ("DCIM") compute paths within the same or tightly coupled memory arrays. A canonical structure stores the bulk of weight matrices in analog (e.g., ReRAM or SRAM-crossbar) arrays, using Kirchoff’s laws or charge-domain summation for parallel multiply-accumulate (MAC) operations. Portioning of either the weight bits (MSB vs. LSB), the data path (mantissa analog, exponent digital), or workflow stages (in-memory analog multiply, backend digital correction) is used to transfer key computation from digital to analog circuits and vice versa.

Partitioning strategies include:

• Bit-width division (MSB–digital, LSB–analog): Digital adder trees or counters compute the most significant bits, while analog accumulation handles least significant bits, e.g., in charge-domain or capacitor arrays (Konno et al., 25 Aug 2025, Yoshioka et al., 2024).
• Functional decomposition: SVD-based matrix factorization, e.g., Hybrid Projection Decomposition (HPD), writes low-rank factors to analog hardware and offloads a residual digital projection for robust correction (Feng et al., 16 Aug 2025).
• Precision-adaptive, data-driven splits: Saliency-aware hybrid designs adjust the digital/analog boundary per data block, maximizing efficiency for low-importance inputs and reserving digital processing for salient data (Chen et al., 2023, Yoshioka et al., 2024).
• Temporal or event-driven coding: Series–parallel nonvolatile cells (e.g., SOT-MRAM) coupled with spiking logic enable time-encoded matrix-vector products, eliminating the need for high-resolution ADCs/DACs (Yu et al., 5 Nov 2025).

These partitioning schemes allow the majority of MACs to be performed at low energy in analog hardware, with a narrow digital pipeline layer ensuring accuracy and noise resilience.

2. Mathematical Formulations and Computational Mapping

A recurrent mathematical motif in hybrid CiM is the singular value decomposition (SVD) or other matrix factorizations to bifurcate the compute path. HPD, for example, factorizes a weight matrix $W$ for an SSM output layer as $W = U \Sigma V^T$, mapping $U\Sigma$ to analog arrays and offloading $V^T$ to the digital domain (Feng et al., 16 Aug 2025). The hybrid output is then: $y = (U \Sigma V^T) h = V [\Sigma (U^T h)]$ where the vector $z = (U \Sigma)^T h$ is first computed via analog CiM and then digitally projected by $V$.

Other notable mathematical constructs include:

• Hybrid floating-point MACs: Mantissa multiplications performed in analog via pseudo-AND circuitry and integrated on switched-capacitor networks; exponent summations and sub-ADD digitally (Yi et al., 11 Feb 2025).
• Quantization-aware training and extreme low-precision partial-sum encoding: Analog matrix-vector multiplies on ternary/binary quantized values, with scale factor accumulation delegated to a digital CiM subarray (Negi et al., 2024).
• FeFET-based QUBO solvers: Inequality constraints are offloaded to analog in-memory comparison, reducing the solution search space, while the quadratic objective is annealed in a FeFET crossbar (Qian et al., 2024).

The selection of boundaries between analog and digital computation is typically co-optimized either by static analysis (e.g., SVD rank truncation, bit split), performance/energy trade-off models, or dynamic data-driven policies (e.g., per-block saliency estimation).

3. Noise, Error, and Robustness Mitigation

Hybrid CiM architectures address error sources that are intrinsic to analog circuits: device conductance variation, line resistances, limited peripheral precision (ADC/DAC), and environmental drifts. Several mechanisms are deployed for robustness:

• Projection-based correction: In HPD, digital projection following analog matrix multiplication re-projects the output, filtering out noise outside the dominant subspace and achieving up to 99.57% reduction in noise-induced perplexity degradation in SSMs (Feng et al., 16 Aug 2025).
• Saliency-aware boundary assignment: By dynamically adjusting which bits are processed digitally vs. analogically, systems can guarantee SNR objectives on a per-MAC basis, discarding or analogizing only those bits whose error will not propagate significantly (Chen et al., 2023).
• Post-hoc digital correction and calibration: Mixed-signal designs may incorporate RISC-V controlled calibration, measuring and linearizing analog transfer functions to achieve 25–45% compute SNR improvement (up to 24 dB) (Numan et al., 18 Jun 2025). Floating-point hybrid architectures deploy post-alignment pipelines and local/global re-normalizations to mitigate fault sensitivity (Bhattacharya et al., 23 Nov 2025).
• Extreme quantization and comparator-only ADC-less integration: Hybrid designs that restrict partial sums to a few quantized levels, mapped to sparse digital accumulate/subtract circuits, replace noisy multi-bit ADCs with low-complexity comparators, passing only the residual accumulations to digital correction paths (Negi et al., 2024).

Empirically, these methods consistently recover baseline accuracy under aggressive noise models and enable graceful accuracy-energy tradeoffs.

4. Circuit and Array-Level Implementations

Key circuit patterns in hybrid CiM include:

• Split-port SRAM: Adding extra transistors and independent word/bit lines to 6T-SRAM enables concurrent digital and analog readouts within the same array (Chen et al., 2023, Konno et al., 25 Aug 2025).
• Switched-capacitor charge sharing: Charge-domain accumulation for LSBs, interfaced via low-resolution, area-efficient SAR- or flash-ADCs (often shared per column group), achieves analog summing with precise, tunable digital merging (Yi et al., 11 Feb 2025, Konno et al., 25 Aug 2025).
• Collaborative digitization: Exploiting parasitic bit-line capacitances, neighboring arrays act as within-memory ADCs/DACs, eliminating standalone ADCs and improving area efficiency by >25× compared to conventional SAR (Nasrin et al., 2023).
• FeFET and SOT-MRAM hybrid logic: In-memory analog inequality filters (FeFET) and hybrid temporal encoding (SOT-MRAM 3T-2MTJ cells) offload specialized non-arithmetic operations for optimization and spiking dataflows (Qian et al., 2024, Yu et al., 5 Nov 2025).
• Digital correction engines: Small digital compute units, per-column adders, or addressable DSP blocks serve as the endpoint for readout digitization, error correction, or digital post-processing.

Peripheral circuits—ADCs, DACs, comparators, sample-and-hold—are designed for minimal area/energy, frequently amortized or even eliminated via hybrid techniques.

5. Compiler, Software, and System Integration

Hybrid CiM’s efficacy hinges on hardware-aware software stacks and compilers capable of exploiting its dual-mode flexibility. Approaches include:

• Dual-mode resource allocation: Hardware abstractions expose arrays that dynamically switch between memory and compute modes. Compilation strategies use mixed-integer and dynamic programming to partition and assign arrays to computation or scratchpad roles, optimizing for varying compute/memory demands across DNN layers, especially in large transformers and LLMs (Zhao et al., 24 Feb 2025).
• Heterogeneous system co-design: Neural Architecture Search (NAS) frameworks co-optimize hybrid CiM with NPUs, mapping compute-bound layers to local digital engines and memory-bound operations to CiM macros. Performance/energy models guide layer assignment, yielding up to 1.34% higher accuracy, 56% lower latency, and 42% energy savings in AR/VR-class edge systems (Zhao et al., 2024).
• Mode-switch meta-operators and IR: Software layers lower the hardware’s mode-switch capability into intermediate representations with explicit meta-operators for compute-memory state transitions, enabling unified orchestration of CIM and memory bandwidth (Zhao et al., 24 Feb 2025).
• In-situ retraining and calibration hooks: Saliency thresholds, quantization parameters, and analog non-ideality compensation can be exposed as co-training variables, tunable within offline retraining pipelines or runtime software calibration routines (Chen et al., 2023, Numan et al., 18 Jun 2025).

6. Benchmarks, Performance, and Trade-offs

The performance envelope of hybrid CiM spans accuracy, efficiency, area, and robustness:

• HPD: 99.57% recovery in noise-induced perplexity degradation; PIQA commonsense accuracy improved by up to 96.67% (Feng et al., 16 Aug 2025).
• HCiM (ADC-less): Energy reductions up to 28× vs 7-bit ADC baselines, <2% Top-1 accuracy loss with 1–1.5-bit partial-sum quantization (Negi et al., 2024).
• Hybrid FP-CiM (SafeCiM): Under single adder-tree MSB fault, accuracy drop constrained to 1% vs. >90% in naive architectures; 49× improved resilience at 10–15% area overhead (Bhattacharya et al., 23 Nov 2025).
• Hybrid-Domain FP-CiM: 1.53× energy gain over digital only, <1% application-level accuracy loss (ResNet/BERT/RetinaNet) for FP8/FP16 inference (Yi et al., 11 Feb 2025).
• Complex MAC hybrid macros: 1.80 Mb/mm² density, 0.435% RMS error, 35 TOPS/W, ~2× more dense and efficient than digital/analog-only designs (Konno et al., 25 Aug 2025).
• HyCiM QUBO: 88–99% crossbar area reduction and nearly 99% optimality success rate by offloading constraint checks to FeFET CiM (Qian et al., 2024).
• OSA-HCIM: Dynamic precision configuration yields 1.95× energy improvement at ≤0.1–5% accuracy loss on CIFAR-100 (Chen et al., 2023).

Parameters such as bit-split (D vs. A), SVD rank, ADC resolution, and data-driven boundary assignment present tunable levers for system designers to navigate trade-off surfaces between accuracy, area/energy, and throughput. Adaptive modes and hybrid functionality routinely enable substantial efficiency gains with only minor, controllable loss in task accuracy.

7. Outlook and Application Domains

Hybrid CiM designs are now routinely employed for:

• Energy-constrained edge inference (mobile vision/audio, IoT)
• Latency- and bandwidth-sensitive inference for LLM and transformer workloads
• Combinatorial optimization (in-memory QUBO solvers with analog constraint filtering)
• AR/VR wearable systems through NPU+CiM heterogeneous fabric (Zhao et al., 2024)
• Always-on and neuromorphic event-based pipelines (spiking MRAM hybrids) (Yu et al., 5 Nov 2025)

Challenges persist in merge-stage overheads, routing congestion, calibration scalability, and compiler co-design for optimal mapping. Open research directions include fine-grained calibration for analog drift, adaptive hardware–software retraining, advanced analog device integration (HDLR, FeFET, SOT-MRAM), and hierarchical memory/compute partitioning for next-generation multi-billion-parameter AI models.

Hybrid CiM stands as a convergent paradigm, capturing a continuous design spectrum spanning from digital precision to analog efficiency, enabled by architectural, algorithmic, and system-level co-optimization (Feng et al., 16 Aug 2025, Chen et al., 2023, Yoshioka et al., 2024, Negi et al., 2024, Yi et al., 11 Feb 2025, Numan et al., 18 Jun 2025, Bhattacharya et al., 23 Nov 2025, Qian et al., 2024, Yu et al., 5 Nov 2025).