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IQM Garnet Quantum Hardware

Updated 2 January 2026
  • IQM Garnet is a 20-qubit superconducting quantum processor that integrates high-fidelity gate operations with scalable, tunable control and advanced materials for hybrid quantum devices.
  • The processor employs a qubit crystal layout with flux-tunable couplers, enabling precise ZZ interactions and low routing distances for efficient quantum error mitigation.
  • It features open, pulse-level control and robust calibration protocols that support state-of-the-art error suppression and optimal quantum control techniques.

IQM Garnet Quantum Hardware refers to a 20-qubit superconducting quantum processor developed by IQM Quantum Computers, designed as a platform for high-fidelity gate operations, scalable architectures, open control interfaces, and materials innovation relevant to hybrid quantum device integration. Garnet processors serve as experimental platforms for both algorithmic benchmarks (GHZ entanglement, randomized benchmarking, quantum volume) and advanced quantum control protocols (e.g., topological dynamical decoupling and optimal control pulse implementations). The device’s architecture, noise performance, classical control infrastructure, software stack, and garnet-compatible substrate technology define its position within current quantum hardware research (Abdurakhimov et al., 2024, Nedev et al., 20 Oct 2025, Malarchick, 16 Nov 2025, Guguschev et al., 25 Aug 2025).

1. Physical Architecture and Device Parameters

The IQM Garnet processor comprises 20 superconducting transmon qubits based on a “qubit crystal” architecture. Qubits are flux-tunable and laid out on a square lattice rotated 45° to the chip edge. Nearest-neighbor coupling is mediated by dedicated, flux-tunable transmon couplers, which provide fully tunable ZZZZ interactions up to ≈50 MHz. This lattice creates a planar, degree-4 connectivity graph, supporting low routing distances and compatibility with surface-code logical qubits (Abdurakhimov et al., 2024).

Individual qubits have bias-tunable frequencies in the 4–6 GHz band; typical anharmonicity is α/2π250\alpha/2\pi \approx -250 MHz, but the exact value for the qubits used in certain experiments is not always reported. The device supports coherence times (across all qubits) with T1T_1 ≈30–60 μs (median ~40 μs) and T2echoT_2^\mathrm{echo} ≈20–40 μs (median ~25 μs). For specific control benchmarking, e.g., qubit 1 in Tₙ dynamical decoupling experiments, measured parameters are T1=44.45T_1 = 44.45 μs, T2=5.88T_2^* = 5.88 μs, and T2echo=18.09T_2^\mathrm{echo} = 18.09 μs, with a single-shot readout error of 2.10% (Nedev et al., 20 Oct 2025).

Readout is achieved using frequency-multiplexed, dispersive measurement via Purcell-filtered resonators, split into three common feedlines. Single-shot readout times are 300–500 ns, with assignment error typically ≈3%. The device wiring comprises 76 superconducting lines, offering individual microwave drive and flux bias to each qubit and coupler.

2. Cryogenic and Control Infrastructure

The Garnet device operates in a Bluefors XLD dilution refrigerator at ≲15 mK base temperature. Drive and flux lines traverse multiple stages of attenuation and filtering to suppress Johnson and RF noise. Magnetic shielding at the mixing chamber minimizes environmental decoherence.

Classical control is implemented via IQM’s modular QCS, built on PXIe. Arbitrary-waveform generation for single-qubit gates uses direct-digital synthesis; flux (two-qubit) control is achieved via fast DACs. Each instrument module is paired with an FPGA for sub-ps synchronized real-time gating, sequencing, and feedback. Readout is amplified at cryogenic temperatures using a TWPA and cascaded HEMTs (Abdurakhimov et al., 2024).

The full software stack includes:

  • Cortex: REST API server for user circuit compilation (Qiskit/Cirq/OpenQASM) and translation.
  • EXA: Python calibration/experiment library with pulse-level access.
  • Station Control: JSON/HTTP–level orchestration interfacing instruments, ensuring persistence of calibration and experimental metadata.

Pulse-level programming is exposed via open interfaces such as “Pulla” (Nedev et al., 20 Oct 2025).

3. Materials Engineering: Garnet-based Substrates for Hybrid Quantum Devices

Ultralow-loss integration with microwave and magnonic systems is facilitated by garnet-type (YSGAG) substrates, supporting epitaxial growth of YIG (yttrium iron garnet) thin films (Guguschev et al., 25 Aug 2025). YSGAG crystals up to 30 mm × 100 mm are produced using the Czochralski technique, with very low rocking-curve FWHM (22 ± 5 arcseconds) indicating high suitability for epitaxy. YIG films grown on these diamagnetic garnets exhibit lattice misfits down to 0.014%, far lower than on conventional GGG substrates.

Ferromagnetic-resonance (FMR) linewidths of YIG/YSGAG remain ≈3 Oe down to millikelvin temperatures, in contrast to YIG/GGG where substrate-induced broadening increases ΔH to ~10 Oe at 2 K. This results in stable, ultralow-damping magnonic channels (Gilbert alpha ~4.5×10⁻⁴). Wafer-scale YSGAG supports planar integration of spin-based, nonreciprocal, and quantum-coherent components. A plausible implication is enhanced fidelity and coherence in hybrid qubit–magnon–photon systems, essential for scalable quantum interconnects.

4. Quantum Control: Native and Optimal Control Pipelines

Garnet provides open, pulse-level access for arbitrary quantum control, supporting both calibrated native gates and user-defined waveforms. All qubits are driven via individually addressable lines. Single-qubit π-rotations are realized via “prx” pulses, calibrated with DRAG-CRF shapes to suppress leakage and drive errors (20 ns duration per π pulse) (Nedev et al., 20 Oct 2025).

Digital-twin–based optimal control is implemented via the QubitPulseOpt framework (Malarchick, 16 Nov 2025). This pipeline builds hardware-representative models by live retrieval of latest calibration data (ωq, α, T₁, T₂) through RESTful API, constructing a Lindblad open-system simulation. GRAPE-based pulse engineering, run within hardware constraints (|Ω| ≤ 2π × 50 MHz, T=20 ns, N=100 slices), achieves 0.9914 simulated gate fidelity vs. 0.334 for a non-optimized Gaussian pulse. Realistic error budgets are injected, but only simulated execution is reported.

These capabilities allow for both hardware-efficient composite control primitives and the investigation of dynamical error mitigation strategies that exploit full calibrated device models.

5. Error Suppression: Topological Dynamical Decoupling Sequences

Garnet was instrumental in experimental validation of Tₙ topological dynamical decoupling (DD) sequences (Nedev et al., 20 Oct 2025). These DD protocols, consisting of n back-to-back π-pulses with analytically prescribed phases (e.g., for even n, ϕk=(k1)(n/2k)n/2π\phi_k = \frac{(k-1)(n/2-k)}{n/2}\pi), enforce two conditions: commutation between pulses and zero vector sum of pulse axes. These properties guarantee exact cancellation of systematic pulse-area errors (to all orders), and increased robustness to detuning.

Experimental 2D robustness scans on Garnet reveal broad fidelity plateaus around nominal pulse amplitude and exact resonance, with plateau width scaling rapidly with n. For T₁₆, the high-fidelity region extends over Δ ≈ ±20 MHz and amplitude error ξ ≈ ±0.15, vastly outperforming CPMG₁₆ (Δ ≈ ±5 MHz). The data support hardware-agnostic realization of topological error suppression, with only state-preparation/measurement (SPAM) errors limiting absolute plateau height (≲99%).

Compared to IBM Heron (ibm_torino), Garnet exhibits similar robustness patterns, despite shorter T₁/T₂. IQM’s native pulse-level access enables finer control for amplitude/detuning mapping and arbitrary phase embedding.

6. Performance Benchmarks and Scalability

Comprehensive performance metrics on Garnet include:

  • Median single-qubit randomized benchmarking errors r1Q5×104r_{1Q} \approx 5 \times 10^{-4} (F_{1Q} ≈ 99.95%)
  • Median two-qubit gate error rCZ5×103r_\mathrm{CZ} \approx 5 \times 10^{-3} (F_{CZ} ≈ 99.5%)
  • Mirror randomized benchmarking error per layer rΩr_\Omega rising from 1.5 × 10⁻³ (n=2) to ~2.5 × 10⁻³ (n=20)
  • Quantum volume (QV) of 25=322^5=32; heavy output probability above the classical threshold by >2σ
  • 20-qubit GHZ state prepared with measured fidelity FGHZ20=0.62±0.02F_\mathrm{GHZ20}=0.62\pm0.02 after readout error mitigation, confirming genuine multipartite entanglement
  • Circuit Layer Operations Per Second (CLOPS) ≈2600

Manufacturing employs high-resistivity Si substrates, Nb ground planes, Al/AlOx/Al junctions (<2% area variation), planar SU-8 crossovers, and Nb air-bridges. Chip-to-interposer flip-chip bonding (indium bumps) is used for control/readout interconnects. Yield exceeds 80% for functional qubits; parameter spread is <10% across runs.

Garnet’s “qubit crystal” architecture is scalable to 54 and 150 qubits by tiling, multiplexing control lines (to ≈2.5 lines/qubit), and transitioning to 3D flip-chip packaging. Projected error budgeting supports scalable quantum volume and volumetric benchmarks.

7. Impact of Garnet Quantum Hardware in Quantum Technologies

IQM Garnet serves as a platform for empirical study of high-fidelity control, scalable device integration, and hardware-aware quantum error mitigation. The open, pulse-level control interface distinguishes it from many comparable commercial systems, enabling rapid translation of theoretical error-correction and optimal-control protocols into experimental validation and benchmarking.

The integration of YSGAG-based substrates offers pathways for chip-scale hybrid quantum devices with ultralow magnonic losses at mK temperatures, supporting circuit quantum electrodynamics and magnon–photon–qubit coupling. The platform’s modular control, open software interfaces, and robust calibration-feedback loops accelerate development and deployment of advanced error-suppressing schemes and quantum optimal control.

IQM Garnet’s benchmarks validate architectural choices (tunable coupler, crystal layout, full-stack orchestration) for NISQ-class algorithms and multi-qubit entanglement, underpinning scalability strategies toward fault-tolerant quantum computation (Abdurakhimov et al., 2024, Nedev et al., 20 Oct 2025, Malarchick, 16 Nov 2025, Guguschev et al., 25 Aug 2025).

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