K-Dimensional Tensor Tiling

• K-dimensional tensor tiling is a method that partitions multidimensional tensors across devices to minimize communication overhead in parallel deep learning.
• It unifies data, model, and hybrid parallelism by formulating the tiling decision as a combinatorial optimization problem with explicit cost modeling.
• The SoyBean system operationalizes these algorithms, demonstrating significant empirical speedups by automatically transforming serial graphs into parallelized execution.

K-dimensional tensor tiling is a systematic method for splitting multidimensional tensors across a set of computational devices such that the overall communication overhead is minimized. Central to parallel deep learning, this framework subsumes data parallelism, model parallelism, and their hybrids by representing parallel strategies as tilings of tensor dimensions. Rigorous treatment of the tensor tiling problem involves combinatorial search over partitionings, explicit modeling of communication costs induced by tiling decisions, and algorithmic solutions that are optimal under practical deep neural network (DNN) architectures. The SoyBean system exemplifies the operationalization of these concepts, transforming serial computational graphs into automatically parallelized forms through optimal tensor tiling (Wang et al., 2018).

1. Formal Definition and Canonical Problem Structure

Let $T$ be a $K$th-order tensor of shape $(n_1, n_2, \ldots, n_K)$. A $K$-dimensional tiling partitions each tensor mode $k$ into $p_k$ equal, disjoint shards, with $p_k \in \mathbb{N}^+$ and each tile of length $n_k/p_k$ (assuming $n_k$ divisible by $p_k$). The full tiling is specified by the tuple $K$0. For $K$1 devices, the partitioning must satisfy $K$2, with devices indexed by $K$3-vectors $K$4, $K$5.

The search space of tensor tilings encompasses all $K$6-tuples of integers $K$7 with $K$8. With increasing device count, the number of possible splits grows combinatorially. Expanding the search space to $K$9 is possible by replicating tiles, though the fundamental challenge remains the optimal split configuration.

2. Communication-Cost Modeling for Operator Graphs

A neural network dataflow graph $(n_1, n_2, \ldots, n_K)$0 consists of tensor operations (edges $(n_1, n_2, \ldots, n_K)$1). Each operator $(n_1, n_2, \ldots, n_K)$2 reads input tensors, applies functions, and produces output tensors. Once a global tiling $(n_1, n_2, \ldots, n_K)$3 is assigned, tensor partitions induce “halo” exchanges or reductions when tiles cross device boundaries.

The total communication volume under a given tiling is formulated as

$(n_1, n_2, \ldots, n_K)$4

where $(n_1, n_2, \ldots, n_K)$5 denotes the per-element data size (in bytes) or operation-specific weights, and $(n_1, n_2, \ldots, n_K)$6 computes the number of elements communicated across devices for operator $(n_1, n_2, \ldots, n_K)$7 under tiling $(n_1, n_2, \ldots, n_K)$8.

Examining matrix-matrix multiplication, each possible tiling (assignment of splits or replications to operands and results) leads to distinct communication patterns, often falling into a small set of “aligned” cases: those incurring zero communication and those requiring a reduction of partial results. The cost function

$(n_1, n_2, \ldots, n_K)$9

governs the conversion and reduction costs between tiling states.

Special parallelization cases correspond to:

• Data parallelism: $K$0 (batch split, other modes replicated).
• Model parallelism: $K$1 for some mode $K$2, all others $K$3 (e.g., channel split).
• Hybrid parallelism: hierarchical multi-mode cuts, e.g., $K$4, which reflects splitting one mode, then another within each subgroup.

3. Globally Optimal Tiling Algorithms

The optimization problem requires joint selection of splits across all tensors due to dependency couplings in $K$5. Independent tiling per tensor is suboptimal. The solution involves a multistage recursion:

a) One-cut (2-way) tiling:

• Transform $K$6 to an undirected variant $K$7, unroll via BFS into levels $K$8.
• Dynamic programming computes $K$9, the minimal communication up to level $k$0 with boundary tensors in tiling $k$1:

$k$2

• For chain-like DNNs, the DP has $k$3 complexity (where $k$4 and $k$5 is small).

b) Recursive $k$6-cut for $k$7 devices:

• Recursively apply one-cut tiling to split into two groups, then within each group solve for $k$8 further cuts.
• Let $k$9. Define recursively: $K$09
• The total communication cost is $p_k$0. The recursion is globally optimal in polynomial time due to cut commutativity (“flattening theorem”) and the greedy property $p_k$1. Overall, complexity is $p_k$2.

4. Canonical Example: 4D Convolution Tiling

Consider a convolutional layer where the activation tensor $p_k$3 and filter tensor $p_k$4. The convolution output $p_k$5 has shape $p_k$6, $p_k$7 for $p_k$8.

Three canonical parallelization/tiling schemes:

• Data parallel ($p_k$9): batch dimension split; no forward communication; backward all-reduce on $p_k \in \mathbb{N}^+$0 ($p_k \in \mathbb{N}^+$1).
• Model parallel ($p_k \in \mathbb{N}^+$2): split in-channel $p_k \in \mathbb{N}^+$3; requires reduce-sum on $p_k \in \mathbb{N}^+$4 and analogous backward exchanges ($p_k \in \mathbb{N}^+$5).
• Hybrid ($p_k \in \mathbb{N}^+$6): first split batch, then split channels within groups; total communication is $p_k \in \mathbb{N}^+$7 (all-reduce), $p_k \in \mathbb{N}^+$8 (per group), total $p_k \in \mathbb{N}^+$9.

Numerical example:

• $n_k/p_k$0, $n_k/p_k$1, $n_k/p_k$2, $n_k/p_k$3, $n_k/p_k$4
• $n_k/p_k$5M, $n_k/p_k$6M bytes
• Data-parallel: $n_k/p_k$7M bytes/iteration, model-parallel: $n_k/p_k$8M, hybrid varies (e.g., $n_k/p_k$9M $n_k$0 $n_k$1M $n_k$2 $n_k$3M for $n_k$4), with further trade-offs depending on $n_k$5, $n_k$6.

The dynamic programming/$n_k$7-cut search automatically explores these hybrid strategies and selects the minimum cost configuration.

5. System Integration: SoyBean Architecture and Empirical Results

SoyBean processes a serial dataflow graph (e.g., from MXNet or TensorFlow) and performs:

• Optimal Tiling: Executes the $n_k$8-cut algorithm to assign tensor-specific tile vectors $n_k$9.
• Device Placement: Maps $p_k$0-index blocks to physical devices, prioritizing hardware hierarchy (first slow links, then internal cuts).
• Graph Rewriting: Expands operators into $p_k$1 sub-operators for corresponding shards and inserts required halo-exchange or all-reduce operations to handle tiling conversions.
• Execution: Dispatches the partitioned graph to the standard dataflow runtime.

Empirical speedups on 8-GPU hardware:

• AlexNet (batch 256): SoyBean achieves $p_k$2 single-GPU speedup, whereas data parallelism requires batch 1024 for comparable scaling.
• VGG (batch 256): SoyBean achieves 5–6$p_k$3 at 8 GPUs; data-parallel peaks at $p_k$4 unless batch $p_k$5 256.
• General result: Across AlexNet/VGG and batch sizes, SoyBean is 1.5–4$p_k$6 faster than pure data parallelism, as it identifies hybrid splits minimizing $p_k$7 (Wang et al., 2018).

6. Implications and Generalization of K-Dimensional Tensor Tiling

• Expressiveness: Any parallelization choice, including data, model, and mixed strategies, can be posed as a $p_k$8-vector $p_k$9 of splits.
• Optimality: For chain-structured DNN graphs, the $K$00-cut algorithm is provably globally optimal in polynomial time.
• Extendability: The tiling set $K$01partition along any mode $K$02, replicate$K$03 can be expanded to support advanced splits (e.g., group convolution partitions), with the dynamic programming/$K$04-cut machinery still directly applicable.
• Systems Integration: Elevating tensor tiling to a primary systems abstraction enables unification and outperformance of hand-tuned parallelism strategies, serving as a functional backend for any dataflow-based deep learning system.

7. Table: Parallelism Schemes under K-Dimensional Tensor Tiling

Parallelism Type	Tiling tuple $K$05	Communication Pattern
Data Parallelism	$K$06	Batch split, all-reduce on weights
Model Parallelism	$K$07	Split one model axis, reduce on output
Hybrid Parallelism	$K$08	Hierarchical, mixes splits and reduces

These canonical strategies exemplify how the tensor tiling framework encapsulates parallelism choices and highlights the trade-offs in communication cost and empirical efficiency (Wang et al., 2018).