Lightweight Simulated Bifurcation

• Lightweight Simulated Bifurcation is a combinatorial optimization algorithm that simplifies the traditional SB method by removing nonlinear terms and quantizing state variables.
• It employs an attention-inspired, graph-topology initializer that reduces iteration counts by up to 80%, significantly accelerating convergence on NP-hard problems like Max-Cut.
• The algorithm is tightly integrated with FeFET-based compute-in-memory hardware, achieving notable speedups and improved solution quality in empirical evaluations.

The Lightweight Simulated Bifurcation Algorithm (light SB) is a hardware-informed, resource-efficient variant of the standard simulated bifurcation (SB) method for combinatorial optimization, specifically targeting large-scale Ising problems. Developed within a ferroelectric compute-in-memory (CiM) framework, light SB is designed to reconcile the algorithmic speed and solution quality of SB with the stringent efficiency and simplicity demands of in-memory hardware, notably FeFET-based crossbar arrays. Its core innovations are the removal of nonlinearities in the update equations and aggressive quantization of internal states, enabling high-throughput, low-latency operation directly on CiM platforms while preserving essential dynamics of the original SB approach (Qian et al., 19 Dec 2025).

1. Mathematical Formulation

The conventional SB algorithm encodes each Ising spin $\sigma_i\in\{+1,-1\}$ as continuous position and momentum vectors $X(t), Y(t) \in \mathbb{R}^N$, updated at each discrete timestep $t$ as: $$Y(t+1) = Y(t) - K [X(t)]^3 - [\Delta - p(t)] X(t) + \zeta J X(t)$$

$X(t+1) = X(t) + \Delta Y(t+1)$

where $J\in\mathbb{R}^{N\times N}$ is the Ising coupling matrix, $\Delta > 0$ is the time step, $p(t)$ ramps up from $0$ to $\Delta$ (an annealing parameter), $\zeta, K$ are constants, and $[X]^3$ indicates element-wise cubic nonlinearity.

The light SB introduces two key simplifications:

• The cubic term is dropped ($K=0$) to eliminate hardware-unfriendly nonlinearities.
• Both $X$ and $Y$ are quantized to ternary values: $X_i, Y_i\in\{-1,0,+1\}$.

Update rules become: $$Y(t+1) \leftarrow \mathrm{Quant}_3\left[Y(t) - (\Delta - p(t)) X(t) + \zeta J X(t)\right]$$

$$X(t+1) \leftarrow \mathrm{Quant}_3\left[X(t) + \Delta Y(t+1)\right]$$

with $$\mathrm{Quant}_3(u) = \max(-1, \min(+1, \mathrm{round}(u)))$$.

2. Algorithmic Workflow and Initialization

Light SB operates within a two-step framework:

1. Attention-Inspired Graph-Topology Initialization: A domain-informed initialization is performed by calculating a “second-order score” for each node:

$$S_i = Q_i^T K V_i = \sum_{j, k} Q_i[j] K[j, k] V_i[k]$$

Here, $K=J$, $V=J$, and $Q$ is the complement mask of $J$’s sparsity pattern. Each initial spin is set as

$$\sigma_i^{(0)} = \begin{cases} +1 & \text{if } S_i \geq \mathrm{mean}(S) \ -1 & \text{otherwise} \end{cases}$$

2. Light SB Iteration: Initialized with $X(0) = \sigma^{(0)}$ and $Y(0)=0$, the quantized update equations are run for $T$ steps, with $p(t)$ linearly ramped as $p(t)=\Delta \cdot (t/T)$. The result is mapped back to $\sigma_i = \mathrm{sign}[X_i(T)]$.

This two-phase approach allows the iteration count $T$ to be reduced by up to 80% compared to conventional SB owing to the informative, topology-driven initialization.

3. Hardware Specialization: Compute-in-Memory Kernels

The light SB algorithm is tightly co-designed with FeFET-based CiM arrays. The main computational kernels are mapped directly to native operations of the hardware:

• Vector-Matrix Multiplication (VMM): $v = J X$ is executed via FeFET threshold-programming per device. The ternary $X$ is applied along array rows/columns in two passes for $X=+1$ and $X=-1$, extracting $v_i$ by current differencing.
• Vector-Matrix-Vector Product (VMV): The attention initializer’s $S_i$ is efficiently realized in a single pass by driving appropriate vectors along bit and source lines and integrating the resulting current.
• Threshold Programming and Reading: All cell writes utilize $\pm 4$V, $1\,\mu$s pulses; readout is via fixed gate bias to yield $I_D \propto$ stored bit.

4. Convergence Behavior and Complexity

Parameter selections follow prior art for SB: $\Delta \approx 0.1$, $\zeta \approx 2.0$, with $K=0$ uniquely to the light SB simplification. Both $X$ and $Y$’s ternary quantization reduces each update to integer operations and a single VMM invocation.

Convergence is rapid on benchmark problems:

• For Max-Cut with $N$ up to $10^5$, light SB converges in $O(100)$ iterations, an 80% reduction from conventional SB due to the attention-based initializer.
• For a $32$-node Max-Cut, the algorithm completes in $20$ iterations ($\approx 900$ ns) on hardware.

5. Empirical Performance

Measured on large Max-Cut graph instances ($1,000 \leq N \leq 10^5$), key performance observations include:

Metric	Gset (N ≤ 7,000)	Yset (N ≤ 10^5)
Time-to-solution speedup vs. GPU-SB	34.5×–160.6×	19.7×–175.9×
Solution quality improvement (max-cut)	+0.53%–6.54%	+0.56%–1.42%
Iteration count reduction (via init)	~80%	~80%
32-node example: iteration/latency	20 iterations/900 ns	—

Attained solutions are consistently superior or comparable to those obtained by GPU-based SB, with both significant improvements in time-to-solution and nontrivial boosts in cut quality due to both algorithmic and hardware optimizations (Qian et al., 19 Dec 2025).

6. Integration and Significance

The light SB algorithm demonstrates that careful removal of nonlinearities and quantized state space, when accompanied by a graph-aware initializer, yields a solver that preserves the essential features of bifurcation-based Ising solvers in a form directly suited to CiM hardware. By mapping the necessary vector-matrix operations to FeFET crossbar primitives and optimizing initialization, it achieves substantial acceleration and quality improvements on NP-hard instances such as Max-Cut, simultaneously addressing central challenges facing in-memory Ising machines—rapid convergence, minimal iteration cost, and solution fidelity at hardware-scale (Qian et al., 19 Dec 2025).