One-Clock Automata

Updated 15 January 2026

One-clock automata are formal models that use a single real-valued clock to manage dense time constraints, ensuring tractability in verification and synthesis.
They exhibit rich variations such as nondeterministic, alternating, and probabilistic forms, linking automata theory with real-time logics and controller synthesis.
The single-clock restriction guarantees decidability in key problems like reachability and model checking, while supporting effective algorithms for learning and parameter synthesis.

A one-clock automaton is a formal computational model that extends the classic automaton paradigm with a single real-valued clock variable, used to express constraints and resets involving dense time or quantitative measurements. One-clock automata admit diverse variants—including nondeterministic, deterministic, alternating, and probabilistic forms—and serve as a foundational class in the theory of timed systems, logic/automata connections, controller synthesis, formal verification, learning, and quantitative analysis. The one-clock restriction is pivotal: it preserves decidability and tractability for many verification and synthesis problems that become intractable or undecidable with two or more clocks.

1. Formal Models and Semantics

The canonical one-clock timed automaton (1-TA) consists of a finite set of locations (states), a single real-valued clock $x$ , and labeled transitions with guards and (possibly) resets. Each transition can be taken if the current clock value satisfies its guard (a conjunction of atomic constraints such as $x\leq c$ or $x \geq c$ , $c\in\mathbb N$ ), and optionally resets $x$ to zero upon traversal. The evolution of the automaton alternates between time-elapse (where $x$ increases uniformly and the system remains in a location as long as its invariant holds) and discrete transitions dictated by edge guards and resets.

In alternating one-clock timed automata (1-OCATA/1-ATA), the transition function maps a location and input to a positive Boolean combination over guarded location and reset formulas (e.g., $\ell$ , $x\bowtie c$ , $x.\gamma$ with $x.\gamma$ denoting a reset before checking $\gamma$ ). Semantics are given via configurations as sets of (location, clock) pairs, supporting branches via the alternation operator (Brihaye et al., 2013, Krishna et al., 2018, Krishna et al., 2021).

Additionally, interval semantics aggregate sets of clock valuations into intervals, which enables symbolic abstraction of the state space and the development of approximation functions that merge clock copies to ensure boundedness in the number of concurrent "copies" tracked during execution (Brihaye et al., 2013).

Parametric timed automata with one parametric clock (1-PTA) generalize this by allowing guards and invariants with parameters—symbols whose values are not fixed a priori but are synthesized or analyzed symbolically (Dai et al., 2018, André et al., 2024, Quaas, 2014). One-clock probabilistic timed automata (1C-PTA) and priced (weighted) timed automata enrich the model with probabilistic choice or accumulated cost, respectively (Sproston, 2020, 0809.0060, 0805.1457).

2. Expressive Power and Logical Correspondence

One-clock automata, especially alternating versions, admit expressive completeness (or tight characterizations) for a variety of timed logics. The classic result is that 1-ATA with loop-free resets are expressively equivalent to the rational metric temporal logic $\mathrm{RatMTL}$ , which extends $\mathrm{MTL[F_I]}$ with regular expression-guarded modalities. A further correspondence exists between $\mathrm{RatMTL}$ and forward $Q^k$ MSO (monadic second-order logic with $k$ variable connectivity), yielding a Büchi–Kamp style logical-to-automata equivalence (Krishna et al., 2018). These relationships persist (with greater expressive power) for extensions to two-way 1-ATA, which correspond to richer fragments (e.g., MSO[<] with guarded metric quantifiers) and can define languages not recognizable by one-way 1-ATA (Krishna et al., 2021).

The interval semantics for one-clock alternating automata enable a direct, singly-exponential translation from metric interval temporal logic (MITL) formulas to classical timed automata, by bounding the necessary number of clock "copies" via interval merging (Brihaye et al., 2013). This ensures that the expressive power of one-clock automata suffices for large classes of real-time logics and their model checking.

3. Decidability and Complexity Frontiers

The restriction to a single clock is essential for decidability boundaries across various problems:

Universality, Reachability, Emptiness: For classical one-clock TA or IRTA, universality and reachability are PSPACE-complete but decidable; with two or more clocks, undecidability can quickly arise (Clemente et al., 2020, Manasa et al., 2010). For parametric TA, emptiness is decidable with one clock but becomes undecidable with three or more parametric clocks (Dai et al., 2018, Quaas, 2014).
Determinization and Minimization: The determinization problem (whether a given 1-TA language can be recognized by a deterministic k-clock TA) is decidable (though non-primitive recursive) when the output automaton has a fixed number $k$ of clocks and the input uses no $\epsilon$ -moves. If $k$ is unbounded, the automaton uses two or more clocks, or $\epsilon$ -transitions are present, undecidability results (Clemente et al., 2020).
Model Checking/Temporal Logics: For one-clock PTAs, model checking WCTL is PSPACE-complete, and for WMTL it is decidable with a single stopwatch cost variable (rates in $\{0,1\}$ ), but any mild extension leads to undecidability (0805.1457). For probabilistic one-clock timed automata and PCTL, the problem remains PTIME-complete (0809.0060).
Synthesis: The timed version of Büchi–Landweber games, as well as controller synthesis (Church synthesis) in games with one-clock automata as winning conditions, is comprehensively undecidable except for certain cases (e.g., when owner and agent coincide for reachability or Büchi acceptance) (Lasota et al., 8 Jan 2026).
Learning and Identification: Active learning of deterministic one-clock timed automata is polynomial-time tractable with a "smart" teacher (that reveals reset information), and of practical complexity with constraint-solving techniques for inferring resets and guards (Xu et al., 2022, An et al., 2019).

4. Parameterization, Quantitative Extensions, and Boundedness

The single-clock assumption admits effective approaches for parameter synthesis, opacity verification, probabilistic analysis, and cost reasoning:

Parameter Synthesis: The parameterized reachability problem for 1-PTA with linear constraints is decidable with feasible region represented as a finite union of polyhedra, and even with polynomial constraints via cylindrical algebraic decomposition (Dai et al., 2018). In more difficult scenarios such as execution-time opacity, a precise decidability frontier exists: for one clock and a single integer parameter, opacity is decidable and precisely characterizable; with more parameters, undecidability arises (André et al., 2024).
Probabilistic Extensions: For one-clock probabilistic timed automata with affine, clock-dependent probabilities and suitable initialization, both quantitative and qualitative reachability become tractable, reducible to interval Markov decision processes (Sproston, 2020, 0809.0060).
Cost Analysis: For priced automata, region abstraction and cost-interval methods ensure PSPACE-completeness for WCTL-model checking as long as costs stay one-dimensional (or one stopwatch), but lead to undecidability otherwise (0805.1457).
Bounding and Abstraction: In alternating semantics, the interval merging technique enables explicit bounding of the number of state "copies" required when simulating MITL formulas in TAs, thus making the interval abstraction an effective symbolic tool (Brihaye et al., 2013).

5. Algorithms and Learning

Learning algorithms for deterministic one-clock TA build upon Angluin’s $L^*$ paradigm but adapt to timing. With a "smart" teacher, the minimal DOTA can be learned in polynomial time via symbolic observation tables and interval partitioning of guards (An et al., 2019). With only access to membership queries for delay-timed words, constraint-solving over possible reset choices renders the problem practically efficient and scalable to moderately complex systems (Xu et al., 2022).

In all algorithmic variants, the region abstraction—a partitioning of $\mathbb{R}_{\geq 0}$ determined by clock constants—plays a critical role in ensuring the effective finiteness of the underlying quotient structures, thus enabling symbolic algorithms for inclusion, equivalence, model checking, and learning.

6. Extensions: Alternation and Two-Way Automata

One-clock alternating automata (1-ATA, 1-OCATA) and their two-way generalizations considerably expand expressive power. 1-ATA with loop-free resets have tight correspondences to temporal logics and fragments of MSO logic (Krishna et al., 2018). Two-way 1-ATA, especially those with reset-free loops and non-adjacency restrictions, are precisely characterized by regular extensions of MTL and guarded MSO fragments, with decidability properties dependent on additional constraints (e.g., "non-adjacency" of intervals), and strictly subsume the expressiveness of one-way alternating variants (Krishna et al., 2021).

Alternating automata with interval semantics yield new translation techniques from MITL to TAs, with bounded clock copies, and facilitate complexity-optimal model checking (Brihaye et al., 2013). These automata serve as the primary vehicle for algorithmic metatheorems on metric temporal logics under timing restrictions.

7. Impact, Open Boundaries, and Research Directions

The theory and algorithmics of one-clock automata delineate a "tractability frontier" for real-time formal models:

Decidability Boundaries: The jump from one to two clocks is sharp: problems such as universality, inclusion, or quantitative model checking become undecidable or EXPTIME-complete for two clocks, but manageable for one (Clemente et al., 2020, 0809.0060).
Logical Connections: One-clock automata form a base case for logical characterizations of timed regular languages, connecting automata, temporal logics, and fragments of monadic second-order logic (Krishna et al., 2018, Krishna et al., 2021).
Algorithmic Metatheorems: The existence of effective region and interval abstractions supports practical algorithms for verification, synthesis, and learning (Brihaye et al., 2013, An et al., 2019, Xu et al., 2022).
Frontier Questions: Open problems persist—such as decidability of parameter synthesis for one clock and two parameters, or the fine border for determinisability and logical separability when some dimensions are unbounded or parametric (André et al., 2024, Clemente et al., 2020).
Practical Implications: The tight bounds on learnability, complexity, and closure properties (e.g., under union, intersection, and complementation for one-clock integer reset automata) underpin the practical tractability of verification tools for real-time embedded systems (Manasa et al., 2010).