Power Amplifiers for RF and Microwave Systems

• Power Amplifiers are key electronic circuits that amplify input signals to drive high-power loads, ensuring optimal efficiency, gain, and linearity in diverse applications.
• Advanced architectures such as Doherty, dynamic load modulation, and multi-way balanced designs enhance performance in mmWave, sub-THz, and broadband systems.
• System-level integration techniques like digital predistortion and EM-aware layout practices are critical for optimizing PA performance in 5G/6G, radar, and quantum computing.

A power amplifier (PA) is a key electronic circuit that provides substantial gain to an input signal in order to drive high-power loads—most commonly, antennas in radio frequency (RF), microwave, and sub-terahertz (sub-THz) transmitters. PAs are essential for maximizing output power, bandwidth, and energy efficiency in wireless communications, radar, sensing, and emerging quantum and mmWave systems. Their design and analysis involve a sophisticated interplay of device physics, circuit topology, electromagnetic (EM) effects, and system-level considerations.

1. Fundamental Design Principles of Power Amplifiers

PAs are universally characterized by their ability to deliver high output power to a load with optimal efficiency, gain, and linearity. These metrics are fundamentally constrained by the device technology (e.g., CMOS, GaAs pHEMT, GaN HEMT), topology (Class A, Class B, AB, C, E, F, Doherty, load modulated balanced, etc.), and the physical effects governing high-frequency operation.

The essential figures of merit in PA design are:

• Gain ($G$): Ratio of output to input power, often specified as $S_{21}$ in dB.
• Saturated Output Power ($P_{\mathrm{sat}}$): Output power at the point where gain compression (often 1 dB) occurs.
• Power-Added Efficiency (PAE): Defined as

$$\mathrm{PAE} = \frac{P_{\text{out}} - P_{\text{in}}}{P_{\text{DC}}}$$

where $P_{\text{DC}}$ is the total DC supply power. High PAE is critical for energy efficiency, thermal management, and battery lifespan.

• Linearity: Quantified by metrics such as Adjacent Channel Power Ratio (ACPR) and Error Vector Magnitude (EVM). Many amplifier classes trade off linearity and efficiency through conduction-angle biasing and waveform shaping.

Impedance matching, parasitic management, and stability are achieved through careful design of transformer-coupled or microstrip-based networks, compensation of device capacitances/inductances, and EM-aware layout strategies (Leea et al., 2024).

2. Power Amplifier Architectures and Advanced Topologies

Diverse PA architectures have been developed to address specific constraints posed by modern communication standards, high peak-to-average power ratio (PAPR) signals, and sub-THz operation:

Class A/AB/C/F/E/J and Load Modulated Topologies

• Class A: Linear, maximal conduction angle (360°), low efficiency.
• Class B/AB: Biased to conduct for 180° (Class B) or an intermediate angle (Class AB, e.g., 210°), balancing efficiency and linearity.
• Class C: Conducts for <$180$°, high efficiency but nonlinear.
• Switching (E, F, J): Use harmonic-tuned switching devices and network synthesis for maximal efficiency, e.g., Class E for IoT, Class J for broadband applications (Cai et al., 2017, Ali et al., 2018, Tehrani et al., 2012).
• Doherty: Main and auxiliary amplifiers with dynamic load modulation, extending efficiency at power back-off; modern designs utilize transformer-based, quarter-wave, and multi-line architectures to further boost performance in the mmWave and sub-THz regime (Wang et al., 15 Nov 2025, Rouhani et al., 2020).

Hybrid, Balanced, and Load-Modulated Structures

• Balanced and Multi-way Load Modulated PAs: Three-way load-modulated balanced amplifiers (H-ALMBA) provide multi-peak efficiency, broadband, and VSWR resilience (Guo et al., 2024).
• Dynamic Load Modulation (DLM): Varactor-based tunable matching networks enhance PAE through real-time impedance adaptation (Tehrani et al., 2012).

Cascaded Structures

• The cascade of several PA stages for systems needing high gain or distributed architecture introduces compounding nonlinearity, managed through stage-wise gain allocation and nonlinear least-squares optimization (Moryakova et al., 18 Mar 2025).

3. Parasitic Effects, Wideband Matching, and EM Layout

At high frequencies (W-band, D-band, sub-THz), device parasitics (gate-source, gate-drain, drain-source capacitances; gate/package inductances) critically degrade gain, efficiency, and bandwidth. Advanced PAs employ:

• Quarter- and Three-Quarter-Wave Transformers: Used for inter-stage and input/output matching with controlled Q for wide bandwidth and minimal area (Leea et al., 2024).
• Wilkinson and Asymmetric Power Combiners: Achieve power combination with isolation and maintain linearity over tens of GHz bandwidth (Leea et al., 2024, Wang et al., 15 Nov 2025, Rouhani et al., 2020).
• On-chip Transformer, Coupled-line, and Artificial TL Networks: Realize compact, low-Q, broadband impedance transformation, and efficient combining in sub-THz CMOS (Lee et al., 20 May 2025).
• EM Simulation and Layout Practices: Include via fences for quasi-TEM propagation, controlled line bends, minimal finger width FETs, and use of mesh cell sizes commensurate with λ/20 to rigorously capture layout parasitics (Leea et al., 2024).

4. Optimization of Power-Added Efficiency and Load Modulation

PAE maximization involves careful selection of bias points, conduction angles, and load-pull derived matching:

• Bias Optimization: Selection of $V_{GS}$ and $V_{DS}$ to reach optimal conduction angle (e.g., $\theta_{\rm cond}\approx210^\circ$ for Class AB) (Leea et al., 2024).
• Load-Pull Tuning: Extraction of $Z_{L,\rm opt}$ at the fundamental, transformed to 50 Ω via multi-section matching (Leea et al., 2024).
• Dynamic Load Modulation: Coordinated control of PA input amplitude, phase, and tunable matching capacitor for trajectory tracking of PAE-optimal load (Tehrani et al., 2012).

For Doherty and load-modulated designs, impedance-scaling networks ensure high PAE at both saturation and power back-off regions by maintaining optimum device load impedances across operating points (Wang et al., 15 Nov 2025, Guo et al., 2024).

5. Behavioral Modeling, Predistortion, and System Integration

High-fidelity behavioral models (memory-polynomial, Volterra, Saleh, Rapp, Ghorbani) are mandatory for PA design and co-design with digital predistortion (DPD) and post-distortion (DPoD) architectures:

• AM-AM and AM-PM Models: Used for both device characterization and DPD/DPoD design in communication and quantum systems (Samara et al., 13 Aug 2025, Jaeger et al., 10 Jan 2026).
• DPD and DPoD Algorithms: Mixed-precision neural networks (MP-DPD), kernel/Volterra-based DPoD, and efficient indirect learning architectures are deployed to compensate memory effects and nonlinearities in massive-MIMO and wideband systems, enabling operation close to saturation without impacting EVM or ACPR (Wu et al., 2024, Schäufele et al., 15 Aug 2025, Prasad et al., 2023).
• System-Level Implications: PA-aware transmit power optimization and PA-switching (PAS) dynamically maximize end-to-end SNDR and augment the spectral efficiency—energy efficiency tradeoff in OFDM/SC-FDMA and ISAC scenarios (Kryszkiewicz, 21 Jan 2025, Joung et al., 2013, Gourar et al., 10 Dec 2025).

6. Performance Metrics, Technology Scaling, and Application Domains

PAs are evaluated on gain, $P_{\mathrm{sat}}$, PAE, 1-dB compression (OP1dB), bandwidth, EVM, and ACPR. Modern mmWave and sub-THz PAs (>95 GHz) in CMOS and III-V show:

Parameter	State-of-the-Art (Example)	Reference
Gain ($|S_{21}|$)	20–35 dB	(Lee et al., 20 May 2025)
$P_{\mathrm{sat}}$	10–30 dBm (often scaled with number of combiners)	(Lee et al., 20 May 2025)
Peak PAE	23–39 % (W-band CMOS/GaAs examples)	(Lee et al., 20 May 2025, Leea et al., 2024)
Bandwidth	20–40 GHz (fractional BW > 30 %)	(Wang et al., 15 Nov 2025)
EVM (DPD-aided)	–38 to –45 dB (for 1024-QAM, OFDM, 160 MHz BW)	(Wu et al., 2024)

PA architectures now target multi-band, load-insensitive, VSWR-resilient operation (e.g., H-ALMBA for 1.7–2.9 GHz, 3-way load modulation), with integrated or easily reconfigurable topologies (Guo et al., 2024). System-level energy savings up to 323% (PAS), and EE improvements of ≈30% (load-adaptive massive MIMO, ET-PA dimensioning) have been reported using holistic circuit–system codesign (Joung et al., 2013, Hossain et al., 2014).

PAs are crucial not only in 5G/6G wireless front-ends and mmWave phased arrays, but also in quantum computing (for high-fidelity gate operations), cell-free massive MIMO, ISAC, satellite, and IoT domains (Jaeger et al., 10 Jan 2026, Jiang et al., 27 Jun 2025, Lee et al., 20 May 2025).

7. Challenges, Trade-Offs, and Future Directions

• Parasitic Mitigation: At ≥100 GHz, parasitics dominate device operation, requiring advanced EM modeling, neutralization (inductive/capacitive), and innovative layout (e.g., skip-layer vias) (Lee et al., 20 May 2025, Leea et al., 2024).
• Linearity-Efficiency Trade-off: High PAPR signals and wideband operation impose strict linearity requirements; PAs must be co-designed with DPD/DPoD and, where feasible, with load-adaptive or switched architectures for maximum system performance (Gourar et al., 10 Dec 2025, Wu et al., 2024).
• Bandwidth vs. Integration Complexity: Scaling bandwidth in transformer/combiner based architectures increases insertion loss and area; PAs for mmWave and 6G demand careful optimization of gain, output power, efficiency, and form factor (Wang et al., 15 Nov 2025, Lee et al., 20 May 2025).
• Resilience and Adaptability: Wideband, multi-band, and mismatch-resilient operation (e.g., H-ALMBA) are key for emerging transceiver architectures, requiring multi-way load modulation, dynamic biasing, and internally reconfigurable PAs (Guo et al., 2024).
• System-Level Co-Design: Efficient integration with antennas, phased arrays, and system architectures is critical given the power, area, and spectral efficiency constraints of next-generation wireless and quantum systems.

Future trends include the adoption of coupled- and zero-degree combiners, digital-radio co-design, EM-codesigned 3D integration (e.g., CMOS+III-V), and DPD/DPoD using mixed-precision and kernel methods for terabit wireless and quantum-classic hybrid communications (Lee et al., 20 May 2025, Schäufele et al., 15 Aug 2025).

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Key References:

• Design of a W-band High-PAE Class A&AB Power Amplifier in 150nm GaAs Technology (Leea et al., 2024)
• 6G communications through sub-Terahertz CMOS power amplifiers: Design challenges and trends (Lee et al., 20 May 2025)
• Varactor-Based Dynamic Load Modulation of High Power Amplifiers (Tehrani et al., 2012)
• A 24-GHz CMOS Transformer-Based Three-Tline Series Doherty Power Amplifier Achieving 39% PAE (Wang et al., 15 Nov 2025)
• Modeling, Analysis, and Optimization of Cascaded Power Amplifiers (Moryakova et al., 18 Mar 2025)
• Digital Predistortion of Power Amplifiers for Quantum Computing (Jaeger et al., 10 Jan 2026)
• Linear Hybrid Asymmetrical Load-Modulated Balanced Amplifier (Guo et al., 2024)
• MP-DPD: Low-Complexity Mixed-Precision Neural Networks for Energy-Efficient Digital Predistortion (Wu et al., 2024)
• Spectral Efficiency and Energy Efficiency of OFDM Systems: Impact of Power Amplifiers and Countermeasures (Joung et al., 2013)