Power Consumption Framework

• A Power Consumption Framework is a multi-layered system designed for precise measurement, modeling, and optimization of energy use in computing systems.
• It combines hardware-level direct measurements with PMC-based statistical modeling and software APIs to support energy-aware design and runtime management.
• These frameworks are applicable to embedded platforms, data centers, and IoT, achieving high accuracy and minimal runtime overhead for energy benchmarking.

A Power Consumption Framework is a multi-layered methodology or system—hardware, software, or both—for the systematic measurement, attribution, modeling, monitoring, and optimization of energy or power usage in computing systems, from embedded platforms to data centers. Such frameworks are essential for energy-aware design, run-time management, optimization, benchmarking, and regulatory compliance. The following sections synthesize the technical details, design methodologies, evaluation metrics, and integrations of state-of-the-art power consumption frameworks in both hardware and software systems.

1. Measurement-Centric Hardware and Embedded Frameworks

A key class of power consumption frameworks is based on direct physical measurement of energy delivered to hardware components. Advanced systems, such as the runtime energy monitoring framework for RISC-V FPGA soft-cores (Scionti et al., 30 Sep 2025), embed precision measurement circuits within the hardware stack:

• Architecture: By interposing a measurement board between an FPGA System-on-Module (SoM) and its carrier, all supply rails (VCCINT, VCCAUX, I/O, DDR, etc.) are forced through shunt resistors for current monitoring. Multichannel ADCs (12-bit, 1 MHz nominal) and analog multiplexers, orchestrated by an on-board microcontroller, digitally encode high-fidelity per-rail current/voltage samples.
• FPGA Data Path: A finite state machine in the FPGA fabric interrogates the ADCs, performs windowed averaging over $K$ samples per channel, timestamps each average with a 100 MHz free-running timer, and memory-maps results into dedicated registers (32-bit data, 64-bit timestamps) accessible via APB/AHB5 interfaces.
• Software Layer: A bare-metal runtime monitoring core reads raw ADC data, reconstructs physical voltages/currents, computes per-rail instantaneous power $P_j(t_i) = V_j(t_i) \times I_j(t_i)$, and accumulates energy $E_j$ by discrete integration. Results are handed to Linux user space and asynchronously published using MQTT (JSON payloads).
• Accuracy: Cumulative error is tightly bounded (current $\leq 1\%$, voltage $\leq 0.2\%$, overall $P_j$ error $\leq 1.2\%$) and validated by cross-calibration (e.g., against Keysight N6705C). Typical system overhead is negligible ($<$1 kLUT, $<$10\% utilization on a small core).
• Scalability and Integration: The design is cluster-scalable, with per-node publish/subscribe over MQTT, centralized aggregation (InfluxDB), and dashboard analytics (Grafana or custom).

This approach eliminates the need for post-hoc model tuning and directly supports design-space exploration and runtime scheduling in FPGA-based, heterogeneous AI systems (Scionti et al., 30 Sep 2025).

2. PMC-Based and Software-Centric Power Modeling

A complementary methodology leverages hardware performance monitoring counters (PMCs) and statistical models to infer subsystem and system-wide power consumption. Representative frameworks (Mazzola et al., 2024, Mazzola et al., 30 Jun 2025) implement this paradigm as follows:

• Offline Modeling: Systems are decomposed into subsystems $d$ (e.g., CPU, GPU), each supporting a set of DVFS (dynamic voltage/frequency scaling) states $P_j(t_i) = V_j(t_i) \times I_j(t_i)$0. For each $P_j(t_i) = V_j(t_i) \times I_j(t_i)$1:
  • The most correlated PMCs $P_j(t_i) = V_j(t_i) \times I_j(t_i)$2 are empirically identified and selected via ordinary least squares regression and Pearson correlation screening.
  • Subsystem power is modeled as

  $P_j(t_i) = V_j(t_i) \times I_j(t_i)$3

  where $P_j(t_i) = V_j(t_i) \times I_j(t_i)$4 is leakage/static power and $P_j(t_i) = V_j(t_i) \times I_j(t_i)$5 are non-negative regression coefficients. - The complete system model aggregates all subsystems for the current DVFS composition:

  $P_j(t_i) = V_j(t_i) \times I_j(t_i)$6

• Kernel-Level Monitoring: The in-kernel “Runmeter” infrastructure tracks and buffers PMC deltas at context switch and at configurable intervals. Using pre-loaded model tables for each DVFS state, instantaneous and integrated subsystem power estimates are computed in fixed-point arithmetic for negligible overhead ($P_j(t_i) = V_j(t_i) \times I_j(t_i)$7 of CPU time per second) (Mazzola et al., 2024).
• Accuracy and Overhead: On heterogeneous testbeds, the combined approach achieves $P_j(t_i) = V_j(t_i) \times I_j(t_i)$8 MAPE for instantaneous power and $P_j(t_i) = V_j(t_i) \times I_j(t_i)$9 for energy, with sub-millisecond update intervals. Integration directly supports API hooks for DVFS scheduling and task-level power capping.

Key limitations include the need for recharacterization if PMC sets or the PMU changes, and model error during rapid workload transitions (Mazzola et al., 2024, Mazzola et al., 30 Jun 2025).

3. Application- and Thread-Level Energy Attribution

Advanced frameworks target fine-grained attribution of energy usage at the process, thread, or container granularity. METRION (Weigell et al., 7 Dec 2025) is exemplary for software energy measurement:

• Architecture: METRION comprises (1) host discovery and idle-power baseline determination, (2) event-capture via eBPF hooks and perf events on context-switch intervals, (3) storage (SQLite adhering to a platform-independent schema), and (4) attribution logic.
• Attribution Model: For each physical component $E_j$0 (CPU, DRAM), total measured energy $E_j$1 is decomposed into idle and active shares. The latter is attributed to threads according to normalized “work” functions (e.g., $E_j$2UCC cycles times frequency scaling, SMT correction, NUMA awareness for CPU; DRAM reads for memory), yielding

$E_j$3

• Evaluation and Overhead: On dual-socket Xeon platforms, METRION achieves $E_j$4 MAPE (CPU), $E_j$5 (DRAM) for workload-specific energy attribution, outperforming existing alternatives by factors of $E_j$6 (Scaphandre, EnergAt). Runtime overhead is below 5\%. Its extensible data model and plugin interface facilitate porting to new architectures and OS platforms.

4. Integrated Frameworks for IoT, Edge, and Cloud

IoT- and cloud-focused power frameworks integrate contextual, predictive, and data-driven approaches for dynamic management and anomaly detection.

• AI-Driven IoT Energy Management (Mruthyunjaya et al., 29 Nov 2025): Modular pipeline integrating LSTM-based long-term forecasting, SVR-based short-term forecasting, kNN anomaly detection, and contextual integration via decision-tree rules. End-to-end, enables real-time, adaptive control actions on edge nodes or at the grid level. Demonstrates MAE $E_j$7 3.6% (SVR), $E_j$8 11% (LSTM), and kNN-based anomaly detection on the top 0.1% of windows.
• Cloud-Native Container Power Accounting (Choochotkaew et al., 2024): Three-stage pipeline (Extract, Isolate, Train) built into Kepler. A key innovation is the dynamic “isolation goodness” metric, which optimizes regression pipelines for per-container power estimation even under hidden hardware, resource crosstalk, and unknown co-tenancy. Empirical results show $E_j$9 improved cross-platform generalizability versus static or heuristic alternative isolation schemes.
• Benchmarking and Validation: Both frameworks emphasize rigorous cross-validation, statistical error metrics, and scalability to virtualized/cloud platforms.

5. Design and Optimization for Communication and Edge Hardware

Frameworks targeting wireless and signal processing systems focus on power minimization under stringent Quality-of-Service (QoS) constraints and dynamic system reconfiguration.

• Subarray Activation for ELAA-ISAC (Cao et al., 28 Jan 2026): Optimization selects an optimal (sparse) set of active subarrays in extremely large antenna arrays, minimizing total power (amplifiers plus per-subarray circuit) while guaranteeing SINR and sensing gain constraints. A successive convex approximation (SCA) solver efficiently finds binary (on/off) subarray schedules, reducing power by up to 50%.
• PASS and RIS Power Models (Xu et al., 3 Jul 2025, Wang et al., 2022): These model the total average power including both transmit (beamforming) and motion/actuation (in PASS, with explicit energy for moving antennas) or structural electronics (in RIS, split into static, drive, and per-cell terms) and further optimize beamforming and placement via ADMM or block coordinate descent. Measurement-validated, component-wise models permit technology-specific design and control.

6. Unified APIs and Framework Integration

Implementation frameworks provide C/C++ or Python APIs, along with CLI and publish/subscribe (e.g., MQTT) interfaces, for programmatic integration, benchmarking, and visualization:

Framework	API Library	Output Channels	OS/Hardware Integration
Runtime Energy Monitor (Scionti et al., 30 Sep 2025)	libenergymon (C/C++)	Memory map, MQTT, Python, CLI	FPGA, Linux
METRION (Weigell et al., 7 Dec 2025)	Python, REST	SQLite DB, Python API, CLI	Linux, x86 (future: cross-arch)
Runmeter (Mazzola et al., 2024, Mazzola et al., 30 Jun 2025)	Kernel, user-space	sysfs, per-task stats	Linux kernel
EACOF (Field et al., 2014)	C/C++ (Provider/Consumer)	Unified device/process checkpoint	macOS, Linux, Windows
KWAPI (Rossigneux et al., 2014)	REST, JSON, ZeroMQ	Ceilometer (OpenStack), RRDs	Large-scale clouds

These APIs, by abstracting hardware specifics and normalizing measurements and models, enable portability across architectures, reproducibility, and integration into orchestration and CI environments.

7. Validation, Benchmarking, and Performance

The adoption and credibility of power consumption frameworks rest on rigorous validation against precision lab equipment, statistical benchmarks, and cross-system studies:

• Direct Measurement Validation: Cross-validation with high-precision power analyzers (e.g., Keysight, oscilloscope) typically yields under 1–2% measurement error (Scionti et al., 30 Sep 2025, Bessa et al., 2017).
• Modeling Accuracy and Overhead: Performance counter-based frameworks demonstrate 3–8% instantaneous MAPE, 1.3–2.5% energy error (Mazzola et al., 2024, Mazzola et al., 30 Jun 2025), and negligible runtime (<1% CPU).
• Use-case Demonstrations: Case studies include ANN inference on custom RISC-V soft-cores (12 mJ/inference, 29% energy reduction with SIMD micro-ops (Scionti et al., 30 Sep 2025)), fine-grained per-thread/process/container energy reporting (Weigell et al., 7 Dec 2025, Choochotkaew et al., 2024), and power-aware scheduling of HPC jobs with Bayesian/machine-learned uncertainty quantification (Storlie et al., 2014).
• Scalability: Architectures such as MQTT-based cross-node web services, modular probe abstraction (EACOF, KWAPI), and clustered collector/aggregator deployment patterns support data center- and grid-scale deployment.

In summary, modern power consumption frameworks span hardware-based direct measurement and software-centric statistical modeling, targeting a spectrum of use cases: run-time system adaptation, design-space exploration, continuous optimization, and regulatory measurement. State-of-the-art systems are evaluated for accuracy, overhead, usability, and extensibility, with formal models, open APIs, and integration capabilities providing the foundation for energy-efficient computing across embedded, cloud, and high-performance platforms (Scionti et al., 30 Sep 2025, Mazzola et al., 2024, Weigell et al., 7 Dec 2025, Mruthyunjaya et al., 29 Nov 2025, Choochotkaew et al., 2024, Cao et al., 28 Jan 2026, Rossigneux et al., 2014, Field et al., 2014, Bessa et al., 2017).