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PPSim: Process Power Simulator

Updated 28 January 2026
  • Process Power Simulator (PPSim) is a simulation framework that models dynamic electrical systems and process-level equipment with high-resolution control.
  • It integrates a modular component library, a control-logic engine, and a scenario manager to support both industrial and HPC power studies.
  • The framework employs detailed component models and real-time data acquisition to achieve accurate power prediction and system validation.

The Process Power Simulator (PPSim) is a versatile simulation framework for modeling electrical power systems, process-level equipment, and their interactions under dynamic scenarios. PPSim has been applied both in industrial-scale electrical network studies and in fine-grained, real-time HPC power modeling, supporting component-level parametrization, high-resolution control strategies, and integration of physical and cyber-physical processes. Its use spans from offshore energy hubs to supercomputing centers, offering a modular simulation approach combining dynamic systems equations, controller logic, and granular scenario management (León-Vega et al., 2024, Omtveit et al., 21 Jan 2026).

1. Architectural Overview

PPSim comprises three principal software layers:

  • Component-Model Library: A repository of parametrized dynamic models (voltage-source converter, synchronous-machine, thyristor rectifier, transformer, static load) that adhere to IEC-style dynamic equations. Each model exposes configuration via built-in parameters such as inertia constants, droop gains, and machine impedances. This library is designed for extensibility and modularity, facilitating reuse across diverse system scenarios (Omtveit et al., 21 Jan 2026).
  • Control-Logic Engine: A modular, PLC-style interpreter that dispatches high-level set-points (e.g., active/reactive power, SoC targets, and equipment state transitions) to each component. The engine includes secondary frequency control, SoC loops, and plant-level coordination, directly supporting operator-in-the-loop studies with sub-second granularity.
  • Scenario Manager: A dynamic scheduling and scripting layer enabling minute-to-year-long simulations, injection of contingencies (N-1 trips, wind time series), real-time data logging, and post-processing for key system metrics (e.g., frequency, SoC, capacity factor). All modules communicate over an internal bus with a nominal 1 ms resolution, supporting high-fidelity system emulation (Omtveit et al., 21 Jan 2026).

2. Component and Process Modeling

PPSim enables process-level and system-level modeling with rigorous mathematical formulations:

  • Wind Turbine Model: Conforms to IEC 61400-27-1 (Type-4) and models aerodynamic conversion, rotor speed dynamics, pitch control, and converter regulation. For turbine ii, the aerodynamic power is calculated as

Paero(t)=12ρACp(λ(t),β(t))vi(t)3,P_{\mathrm{aero}}(t) = \frac{1}{2}\rho A C_p(\lambda(t),\beta(t)) v_i(t)^3,

where ρ\rho is air density, AA rotor area, CpC_p the power coefficient, λ\lambda the tip-speed ratio, and β\beta the pitch angle. Rotor inertia and pitch actuator dynamics are explicitly modeled (Omtveit et al., 21 Jan 2026).

  • Electrolyzer Model: Each train contains two 2.5 MW stacks on a 12-pulse rectifier. The stack's I–V characteristic is Vcell(I)=Erev+rΩIV_{\mathrm{cell}}(I) = E_{\mathrm{rev}} + r_\Omega I and electrical losses, ramp-rate limitations (P˙ely(t)Rely|\dot P_{\mathrm{ely}}(t)| \leq R_{\mathrm{ely}}), and master–slave/synchronized control are included.
  • BESS Model: Includes SoC dynamics, grid-forming virtual synchronous machine (VSM) swing equations, and frequency/voltage droop control. SoC evolution follows:

dSoCdt=PBESS(t)Eratedηc/d\frac{d\,\mathrm{SoC}}{dt} = -\frac{P_{\mathrm{BESS}}(t)}{E_{\mathrm{rated}}\,\eta_{c/d}}

with ηc/d\eta_{c/d} round-trip efficiency and EratedE_{\mathrm{rated}} capacity (Omtveit et al., 21 Jan 2026).

  • Process-Level Power: In HPC scenarios, PPSim can embed regression-based process power models derived from instruction mix and utilization features, as described in EfiMon (León-Vega et al., 2024).

3. Data Acquisition and Feature Engineering

PPSim's methodology for process power estimation (notably for supercomputing contexts) is based on noninvasive, real-time data collection:

  • Observers: Modules such as ProcStatObserver, PerfAnnotateObserver, RAPLMeterObserver, and IPMIMeterObserver gather per-process CPU utilization, instruction histograms (across eight instruction families), RAM usage, and system/socket/PSU-level power (León-Vega et al., 2024).
  • Temporal and Spatial Resolution: Sampling intervals (Δt\Delta t) range from 100 ms to 1 s. Observers align all readings on a common timescale and spatially tag process-level vs. socket-level metrics.
  • Feature Construction: PPSim constructs normalized instruction histograms hk(p)(t)h_k^{(p)}(t) and CPU utilization wp(t)w_p(t) for each process pp, aligned to a grid and optionally smoothed for robustness against measurement noise (León-Vega et al., 2024).

4. Mathematical Formulation of Process Power Models

At process level, PPSim applies an additive regression model decomposing system power Psystem(t)P_{\mathrm{system}}(t) into static and dynamic components:

  • System-level decomposition:

Psystem(t)=Pstatic+p=1NpPp(t)P_{\mathrm{system}}(t) = P_{\mathrm{static}} + \sum_{p=1}^{N_p} P_p(t)

  • Per-process dynamic power:

Pp(t)=k=18γkσk(hk(p)(t),wp(t),Nc)P_p(t) = \sum_{k=1}^8 \gamma_k \cdot \sigma_k( h_k^{(p)}(t), w_p(t), N_c )

where kk indexes instruction families, hkh_k the normalized retired instruction count, wpw_p the process-level CPU utilization, NcN_c the total number of cores, γk\gamma_k weights fitted with Non-Negative Least Squares, and σk\sigma_k is the shape function defined as: - For vector arithmetic/memory: σk=hkln(Ncwp+1)\sigma_k = h_k \cdot \ln(N_c w_p + 1) - For others: σk=Nchkwp\sigma_k = N_c h_k w_p

Parameter fitting is performed separately per hardware architecture, using K-fold cross-validation, resulting in 2-5% typical prediction error of per-process power, and a maximum deviation of 4.4% on AMD and 2.2% on Intel in shared environments (León-Vega et al., 2024).

5. Simulation Workflows and Application Domains

The simulation workflow in PPSim comprises stepwise scenario execution, control-loop updating, and event-driven recalculation of power/process states:

  • Simulation timestep: Matches data acquisition rates, typically 250 ms to 1 s.
  • Inputs/outputs: Per-process instruction mix and CPU utilization drive per-tick power prediction; component models receive control commands from the scenario manager/control-logic engine.
  • Event handling: Change-driven update logic reduces computational overhead; for 1000 processes at 500 ms, less than 1 ms CPU overhead on a modern core (León-Vega et al., 2024).

Application examples include:

  • CleanOFF Offshore Hub: PPSim was used for real-time simulation of a wind/green hydrogen platform, supporting design optimization of BESS sizing, analysis of wind farm turbulence, and the impact of electrolyzer ramp speed and coordination. Fast-ramp + synchronised electrolyzer control reduced the required BESS power rating by up to 70% compared to slow-ramp sequential strategies (Omtveit et al., 21 Jan 2026).
  • HPC Power Accounting: PPSim enables granular attribution of power to individual processes, supporting power-aware scheduling, what-if analysis, and node-subsystem accounting beyond the granularity of node-level metering (León-Vega et al., 2024).

6. Validation, Limitations, and Extensibility

Validation

  • Testbeds: Validation includes both industrial electrical network hardware (e.g., 2×AMD EPYC/Intel Xeon nodes for HPC; scaled 66 kV main bus for CleanOFF) and process benchmarks (dgemm, daxpy, stream, synthetic workloads).
  • Benchmarks: Validation spans isolated and co-executed process scenarios, control strategy impact assessment, and contingency injection (wind-turbine or load trips).
  • Performance: Predictive accuracy for process-level models is within a 2.2–4.4% envelope; system-level dynamic response fidelity is matched to empirical wind- and load-time series (León-Vega et al., 2024, Omtveit et al., 21 Jan 2026).

Limitations

  • Linearity: Current models assume linear, additive contributions of process power; contention effects are not modeled.
  • Static power constancy: PstaticP_{\mathrm{static}} is held fixed over time/workload, and thermal/fan dynamics are omitted.
  • Feature sufficiency: Only instruction mix and CPU utilization are modeled explicitly; memory bandwidth, RAM power, and DVFS behaviors are not parameterized in current public implementations.

Extensibility

  • Hardware support: Model APIs are compatible with new analytic σk\sigma_k functions, extended instruction sets (e.g., GPU via NVMLObserver), heterogeneous hardware, and dynamic fan/thermal modeling.
  • Machine learning: Potential exists to replace linear NNLS with random forests, neural nets, or nonparametric regressors, presuming access to sufficient training data.
  • Scenario expansion: The scenario manager allows for long-term stochastic analysis (year-scale Monte Carlo), system upscaling, and integration with external process simulators for hydrogen, fuel cell, and thermal loads (León-Vega et al., 2024, Omtveit et al., 21 Jan 2026).

7. Parameter Tables and Boundary Conditions

Selected parameters and modeling assumptions as used in published studies:

Subsystem Key Model Parameters/Assumptions Source
Wind Farm 8 × 8 MW, Type-4 turbines, spacing 5DD, Kaimal spectrum, LL=340m (Omtveit et al., 21 Jan 2026)
Electrolyzer 7 × 5 MW trains, ramp: 11 s/706 s, sequence vs. sync control (Omtveit et al., 21 Jan 2026)
BESS Power: 10 or 30 MW, Energy: 10 MWh, VSM grid-forming control (Omtveit et al., 21 Jan 2026)
HPC Process γk\gamma_k (per architecture), β0\beta_0, 8-feature instruction mix (León-Vega et al., 2024)

Boundary conditions include fixed network voltage at 66 kV, process configurations per experimental run, and system states reset via the scenario manager. Evaluation in both isolated and shared-core environments ensures model applicability across use cases.

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