REAP-cache: Preventing Read Error Accumulation

• REAP-cache is a cache architectural enhancement that prevents the accumulation of read-disturbance errors in STT-MRAM by ensuring every cache block is corrected on each access.
• It employs parallel ECC decoders for all fetched lines, eliminating the error build-up from concealed speculative reads without increasing access latency.
• Quantitative evaluations show that REAP-cache improves cache reliability by up to 171× with less than 0.8% area and about 2.7% average dynamic energy overhead.

The Read Error Accumulation Preventer cache (REAP-cache) is a cache architectural enhancement for Spin-Transfer Torque Magnetic RAM (STT-MRAM) caches, designed to eliminate the accumulation of read-disturbance errors. STT-MRAM is considered a strong candidate to replace SRAM in on-chip cache applications due to its scalability, high density, non-volatility, and negligible leakage power. However, the reliability of STT-MRAM caches is fundamentally limited by the phenomenon of read-disturbance: when the read process itself has a nonzero probability of altering the stored data, especially in set-associative caches where speculative, “concealed” reads can cause errors to accumulate undetected until they become uncorrectable. REAP-cache modifies the cache’s read path and error-correcting workflow to ensure immediate correction of every cache block on every read, thereby eliminating this error accumulation and significantly improving reliability while incurring minimal area and energy overhead (Cheshmikhani et al., 1 Jan 2026).

1. Read-disturbance Accumulation in STT-MRAM

STT-MRAM cells are implemented using @@@@1@@@@ (MTJs), where reading involves applying a small current ($I_{\rm read}$) across the MTJ. Due to the stochastic nature of magnetization switching, this read current can inadvertently flip the stored value—specifically, a ‘1’ can become a ‘0’ if the current’s direction and magnitude cross certain thresholds. This effect is termed a “read-disturbance error.”

For a single cell and a read of duration $t_{\rm read}$, the disturbance probability follows:

$$P_{\rm RD\text{-}cell} = 1 - \exp\Bigl(-\,t_{\rm read}/\tau\;\exp\bigl(-\,\Delta\,(I_{\rm read}-I_{C0})/I_{C0}\bigr)\Bigr)$$

where $\tau$ is the attempt period (≈1 ns), $I_{C0}$ is the zero-Kelvin switching current, and $\Delta$ is the thermal stability factor.

When reading an $n$-bit cache line, only cells storing ‘1’ are susceptible to flipping. Under a single-error-correcting, double-error-detecting (SEC-DED) ECC scheme, the block’s probability of remaining correct after one read is

$$P_{\rm corr\text{-}blk} = (1 - P_{\rm RD\text{-}cell})^{n} + n\,P_{\rm RD\text{-}cell}\,(1-P_{\rm RD\text{-}cell})^{n-1}$$

Modern set-associative caches read all $k$ ways in parallel for tag comparison, shielding only the requested block with ECC, while discarding other $k-1$ blocks without error checking. Each such “concealed” read introduces additional disturbance. Across $N$ reads before a block is checked with ECC, the uncorrectable error probability increases by several orders of magnitude compared to a single read ($N=1$). For example, with $n=100$, $P_{\rm RD\text{-}cell}=10^{-8}$, and $N=50$, the uncorrectable error probability $P_{\rm err}^{\rm acc}$ rises to $1.3\times10^{-9}$ compared to $5.0\times10^{-13}$ for a single read.

2. REAP-cache Architecture and Operational Mechanism

REAP-cache addresses the root cause of error accumulation by reorganizing the ECC checking in the cache read path. In traditional cache architectures, after reading $k$ lines in parallel, a $k$-to-1 multiplexer selects the requested line, and only this line passes through a single ECC decoder. The non-requested lines are discarded without correction, allowing errors from speculative reads to accumulate.

REAP-cache modifies this flow by running all $k$ fetched lines through $k$ parallel ECC decoders before entering the multiplexer. Thus, every block read (speculative or actual) is checked and corrected for single-bit errors on every read access. Key features include:

• Replication of ECC decoders: one per way, typically $k=8$ for an 8-way set-associative cache.
• No need for new tag bits, per-block counters, or additional scheduling.
• Tag comparison, array read, and ECC decoding occur in parallel, preserving cache access latency.

Algorithmically, the maximum number of disturbances any block can accrue before being checked is limited to just a single read, eradicating concealed read accumulation and substantially reducing the risk of uncorrectable errors.

3. Comparative Reliability Analysis

The improvement in reliability can be quantified by contrasting error probabilities for conventional and REAP schemes. For $N$ reads:

Conventional (with accumulation): $$P_{\rm corr}^{\rm conv}(N) = (1 - P_{\rm RD})^{Nn} + Nn\,P_{\rm RD}\,(1-P_{\rm RD})^{Nn-1}$$

$$P_{\rm err}^{\rm conv}(N)=1-P_{\rm corr}^{\rm conv}(N)$$

REAP-cache (no accumulation): $$P_{\rm corr}^{\rm REAP}(N) = \left[(1 - P_{\rm RD})^{n} + n\,P_{\rm RD}\,(1-P_{\rm RD})^{n-1}\right]^N$$

$$P_{\rm err}^{\rm REAP}(N)=1-P_{\rm corr}^{\rm REAP}(N)$$

In a representative scenario ($n=100$, $P_{\rm RD}=10^{-8}$, $N=50$), $P_{\rm err}^{\rm conv}(50)\approx1.3\times10^{-9}$, while $P_{\rm err}^{\rm REAP}(50)\approx2.6\times10^{-11}$. This highlights the magnitude by which concealed reads dominate the error profile in conventional caches and demonstrates REAP-cache's efficacy in eliminating this channel.

4. Quantitative Evaluation and System Overheads

The reliability experiments utilize full-system gem5 simulation across all 29 SPEC CPU2006 workloads, modeling a two-level cache with L1 (SRAM), L2 (2 MB STT-MRAM, 8-way set-associative, 64 B lines, SEC-DED ECC). Uncorrectable errors are injected and modeled probabilistically based on the derived $P_{\rm RD\text{-}cell}$.

• Mean Time To Failure (MTTF): Under typical workloads, conventional STT-MRAM L2 caches experience failures in milliseconds to seconds, while REAP-cache extends MTTF by an average of 171× (up to $>1000\times$ in the most memory-intensive cases). Even in the least favorable workload (mcf), the improvement is approximately 7.9×.
• Area overhead: Implementation requires $k-1$ additional ECC decoders per set ($<0.8\%$ total area increase in an 8-way, 2 MB cache).
• Energy overhead: Dynamic energy increases by approximately 2.7% on average (maximum 6.5%, minimum ~1.0%), as the ECC decoders operate in parallel with no additional cycle penalty.
• Performance: No increase in cache access latency or pipeline critical path, since tag comparison and decoding are parallelized.

Metric	Conventional STT-MRAM	REAP-cache (relative)	Overhead Type
L2 MTTF	ms–s	$+171\times$	Reliability
Area	baseline	$+<0.8\%$	Silicon
Dynamic Energy	baseline	$+2.7\%$ avg	Power
Access Latency	baseline	none	Performance

5. Design Trade-offs, Limitations, and ECC Interactions

REAP-cache is orthogonal to the choice of ECC code. While it is most effective in conjunction with single-bit correcting codes such as SEC-DED, it can be paired with stronger multi-bit ECCs if required by process variation or reliability margins. Unlike RESTORE-after-read techniques—which impose a writeback penalty on every read cycle—REAP-cache requires only additional logic for parallel ECC decoding, with no need for tag bits, counters, or restore operations.

The architecture does not address the rare event of multi-bit upsets within a single read cycle; such events remain uncorrectable under single-bit ECC, but are vanishingly rare given $P_{\rm RD\text{-}cell}$ is extremely small and only one read’s disturbance is relevant per access. In aggressive technology corners (i.e., higher $I_{\rm RD}$ or lower $\Delta$), REAP-cache can coexist with stronger ECC or write-verify schemes for further mitigation.

A plausible implication is that REAP-cache shifts the primary error channel from speculative read accumulation to intrinsic cell-level and ECC-correctable errors, narrowing the reliability bottleneck and delaying the need for more complex error correction methods.

6. Context and Significance

REAP-cache directly addresses the architectural source of reliability degradation in set-associative STT-MRAM caches due to speculative reads, enabling system designers to leverage STT-MRAM’s density and energy profile without incurring large reliability penalties or complex ECC deployments. This approach provides a quantifiable, order-of-magnitude improvement in operational robustness (as measured by MTTF) at negligible performance and cost impact, and does so by a minimal and targeted hardware modification (Cheshmikhani et al., 1 Jan 2026). As the adoption of non-volatile memory technologies continues to expand, such schemes offer a practical path for marrying emerging memory technologies with aggressive cache architectures.