Silicon-on-Insulator Platform

Updated 24 January 2026

Silicon-on-insulator (SOI) is a layered system with a thin silicon device layer atop a buried SiO₂, enabling high optical confinement and dense integration.
Its compatibility with deep-UV and e-beam lithography allows fabrication of advanced photonic components like nanocouplers, modulators, and on-chip light sources using standard CMOS processes.
SOI supports versatile applications including quantum state generation, nonlinear optics, and topological photonics, making it essential for scalable on-chip optical systems.

The silicon-on-insulator (SOI) platform is a foundational technology for integrated photonics, quantum optics, topological photonics, and high-speed optoelectronics. SOI consists of a thin crystalline silicon device layer separated from the silicon substrate by a buried oxide (BOX) layer, typically made of SiO₂. The high index contrast between silicon (n ≈ 3.48 at 1550 nm) and SiO₂ (n ≈ 1.44) enables strong optical confinement, dense integration, and compatibility with standard CMOS manufacturing. SOI technology supports advanced device architectures, including nanophotonic circuits, quantum state generators, electro-optic modulators, photonic crystal structures, and on-chip light sources.

1. SOI Wafer Stack, Materials, and Fabrication

SOI wafers are composed of a handle silicon substrate, a BOX layer of SiO₂ (typically 2–3 μm thick), and a device silicon layer (commonly 220 nm thick for photonics). Devices and circuits are defined in the top Si layer via deep-UV or e-beam lithography followed by anisotropic plasma etching. Subsequent steps, including ion implantation, deposition of claddings (e.g., PECVD SiO₂), and metallization, are compatible with CMOS foundry processes (Allo et al., 22 Mar 2025).

Key SOI stack parameters from mainstream foundry flows:

Device Si Thickness	BOX Thickness	Top Cladding	Typical Use Case
220 nm	2-3 μm	SiO₂	Passive/active photonics
40–450 nm	2 μm	Si₃N₄/SiO₂	Nanolaser/cavity

SOI is inherently compatible with wafer-scale fabrication, enabling integration of modulators, detectors, nonlinear sources, and even nanowire lasers. Foundry-scale flows allow post-processing such as color center creation (via MeV Si⁺ implants and low-T anneal) directly on completed chips (Allo et al., 22 Mar 2025).

2. Inverse-Designed and Conventional Passive Photonic Components

SOI is the dominant platform for both conventional (grating couplers, strip/rib waveguides, MMI splitters) and inversely-designed (topology-optimized) nanophotonic components. The ultra-high index contrast enables compact devices with ultrashort bends and low insertion loss.

A representative topology-optimized vertical fiber-to-chip coupler achieves –0.35 dB insertion loss at 1550 nm with a 14 μm × 14 μm footprint, far smaller than state-of-the-art grating couplers (typically ≥200 μm × 14 μm). The optimization process discretizes the Si layer into a pixel grid with a continuous density variable ρ(x,y) ∈ [0,1], which is regularized via filtering and Heaviside projection to enforce ≥150 nm feature sizes compatible with standard CMOS fabrication (Huang et al., 2024).

Simulation utilizes 3D FDTD with a uniform 20 nm grid and models the bottom reflector as a perfect electric conductor placed below the 2 μm BOX. The final device employs two Si etch depths: a full etch for waveguides and a 70 nm shallow etch for the coupler region. The predicted performance metrics are:

Peak coupling efficiency: η = 92.2% (–0.35 dB) at 1550 nm
3-dB bandwidth: Δλ ≈ 35 nm (1540–1575 nm)
Lateral alignment tolerance (3 dB): Δx ≈ ±3.5 μm
Directionality: >95% of input coupled upward, substrate leakage ≪1% due to the reflector

Compared to conventional grating couplers, topology-optimized devices exploit the full design space for minimal footprint, robust CMOS compatibility, and improved coupling efficiency (Huang et al., 2024).

3. Quantum State Generation and Nonlinear Photonics

The SOI platform supports advanced quantum photonics architectures via on-chip integration of nonlinear photon sources and programmable filters. A recent architecture employs a cascade of SOI-integrated components:

An N-tap FIR (finite impulse response) pulse shaper, implemented in a 490 nm × 220 nm SOI strip waveguide, splits a Gaussian pump into N arms with independent amplitude and phase control.
The recombined pulse feeds an MZI-coupled microring resonator source, also in SOI, designed for spontaneous four-wave mixing (SFWM).

The FIR pulse shaper transfer function:

$H(\omega) = \sum_{n=1}^N \alpha_n e^{j(\phi_n - n\omega\tau)}$

controls both the amplitude and phase across the pump spectrum, enabling programmability of the joint spectral amplitude (JSA) of the photon pair source.

By shaping the pump and utilizing the resonator's spectral response, maximally entangled time-frequency mode (TFM) states can be generated in dimensions d = 2,3,4, with simulated output fidelities F = 0.950, 0.954, 0.971, respectively (2504.09957). The SOI platform's high index contrast allows compact device geometries (bend radii 10–50 μm), low-power tuning, and monolithic integration of both linear (pulse shaping) and nonlinear (SFWM) functions. Scalability is influenced by waveguide propagation loss (1–3 dB/cm), split/combiner loss (~15 dB total shaping loss), and thermal crosstalk among densely packed phase shifters.

4. Monolithic and Hybrid Sources: Nanowire Lasers and Color Centers

SOI's indirect bandgap limits efficient light emission. Nevertheless, advances in heterogeneous and monolithic integration have enabled on-chip sources:

III–V Nanowire Array Lasers: Monolithic growth of InGaAs/InGaP core/shell nanowire arrays directly on SOI (via selective-area MOCVD on Si₃N₄-masked SOI(111)) forms photonic crystal nanobeam cavities with high modal Q (Q_calc > 8 × 10⁴, Q_meas ≈ 1.15 × 10³ at threshold) and confinement factor up to Γ = 0.64. Lasing is achieved at room temperature, with cavity modes efficiently coupled (>50%) to SOI waveguides owing to near-field overlap. Standard device layers are 40–220 nm Si, BOX 2 μm, compatible with PIC architectures (Kim et al., 2017).
Color Center Emitters: Creation of optically active W-centers in commercial 220 nm SOI is realized via back-end-of-line (BEOL) MeV Si⁺ implantation and low-temperature anneal. W-center zero-phonon-line emission (λ₀ = 1218 nm, FWHM ≈ 1 nm) can be extracted with ~2× enhancement using on-chip circular Bragg grating structures. Ensemble brightness is ~2×10⁴ counts/s under 90 μW optical pump, approximately 64% of in-house processed wafers, but fully foundry-compatible. Approach does not require FEOL changes and is suitable for 300 mm wafer-scale implementation (Allo et al., 22 Mar 2025).

These technologies enable heterogeneous and monolithic light sources for on-chip communications, quantum optics, and classical photonics.

5. Topological, Nonlinear, and Superlattice SOI Derivatives

SOI platforms support advanced functionalities beyond passive and active photonics, including topological, nonlinear, and electro-optic effects:

Valley Photonic Crystals: An SOI slab (220 nm device Si, 2 μm BOX) patterned with a 2D honeycomb lattice (lattice constant a = 385 nm) and two sizes of air holes supports a valley-dependent TE bandgap (1360–1492 nm). Breaking inversion symmetry produces large Berry curvature at K/K′ and topological valley edge states protected against backscattering, even at subwavelength scales (<10 μm). Multi-bend interfaces (Z/Q-shaped) exhibit flat-top transmission and >90% bend efficiency within the bandgap. Bearded-stack interfaces combined with subwavelength microdisk vortex generators enable valley-chirality-locked unidirectional edge excitation and subwavelength topological routing (He et al., 2018).
Hybrid Electro-optic Modulators: Integration of a thin-film lithium niobate (LN) layer onto passive SOI circuits via BCB bonding yields high-performance Michelson interferometer modulators. Electro-optic phase shifting occurs in the LN layer (phase shifter voltage–length product V_πL = 1.2 V·cm), with low on-chip insertion loss (3.3 dB), and EO bandwidth of ~17.5 GHz. The architecture exploits vertical adiabatic couplers to link the SOI and LN layers, with GSG electrodes optimizing mode-overlap for GHz operation (Xu et al., 2019).
Superlattice-on-Insulator (SLOI): Short-period III–V/Si or II–VI/IV superlattices (SL), e.g., (GaP)₂/(Si₂)₁, (AlP)₂/(Si₂)₁, (ZnSe)₂/(GaAs)₇, are grown by MBE, wafer-bonded onto SiO₂/Si, and patterned into rib/strip waveguides. These exhibit theoretically large Pockels r₃₃ (up to 115 pm/V), low VπL (<0.1 V·cm), sub-fJ/bit energy, and high modulation bandwidths (>50 GHz). Tight-binding models and full-vectorial FEM inform device design. SLOI is compatible with monolithic integration of PIN/APD detectors and standard photonic workflows (Leonardis et al., 2022).

These approaches expand SOI capabilities into regimes of topologically protected transport, high-speed, and low-power modulation, nonlinear optics, and multi-functionality.

6. Integration, Scalability, and Roadmap

The SOI platform is characterized by:

Monolithic and hybrid integration: SOI supports growth or bonding of III–V nanostructures, thin-film LN, color center engineering, and superlattice transfer.
CMOS compatibility: All steps from patterning, etch, and cladding to BEOL metal routing and post-processing (e.g., Si⁺ implant for W-centers) deploy standard tools and protocols (Allo et al., 22 Mar 2025, Huang et al., 2024).
Wafer-scale and foundry-enabled processing: Demonstrated for PICs, color center sources, and hybrid modulators. BEOL-only strategies avoid foundry flow interruptions and are scalable to 300 mm wafers.
Minimal feature sizes and process controls: Advanced designs enforce ≥150 nm lithographic features, use shallow and full etch steps, and deploy thermal tuning or BCB thickness control for device yield.
Integration of classical, quantum, and nonlinear photonics: On-chip routing, multiplexing, quantum state generation, and high-speed modulation are realized in a unified photonic platform (2504.09957, Leonardis et al., 2022).

The platform’s challenges include propagation loss in high-confinement Si, process variability, and thermal crosstalk—areas under continued optimization in both foundry and academic settings.

References:

(Huang et al., 2024) Compact Inversely-Designed Vertical Coupler with Bottom Reflector for Sub-Decibel Fiber-to-Chip Coupling on Silicon-on-Insulator Platform
(2504.09957) Programmable time-frequency mode encoded quantum state generator for silicon-on-insulator platform
(Allo et al., 22 Mar 2025) Photoluminescent colour centres on a mainstream silicon photonic foundry platform
(He et al., 2018) A Silicon-on-Insulator Slab for Topological Valley Transport
(Xu et al., 2019) Lithium Niobate Michelson Interferometer Modulator on Silicon-On-Insulator Platform
(Kim et al., 2017) Monolithic InGaAs nanowire array lasers on silicon-on-insulator operating at room temperature
(Leonardis et al., 2022) High-performance Pockels-effect modulation and switching in silicon-based ... superlattice-on-insulator integrated circuits