Source-Degenerated Current Mirror (SDCM)

• SDCM is a current mirror topology that employs a source degeneration resistor to introduce local negative feedback for improved current transfer and noise suppression.
• Small-signal analysis reveals that degeneration reduces the effective transconductance by approximately 1/(1 + gm·RS), which modulates both output resistance and noise characteristics.
• The design trade-offs include a voltage headroom penalty offset by a 7.95% noise reduction and a 32.4% power saving in 28 nm CMOS IA applications, underscoring its practical significance.

A source-degenerated current mirror (SDCM) is a current mirror topology in which a degeneration resistor is incorporated in series with the source terminal of the mirroring transistor. This structure introduces local negative feedback that modulates both current transfer accuracy and noise characteristics. In advanced CMOS instrumentation amplifier (IA) designs, particularly those targeting low-power and low-noise applications such as bioimpedance sensing, SDCMs serve as crucial building blocks to balance input-referred noise with available voltage headroom, as quantitatively demonstrated by a 7.95% input-referred noise reduction in a 28 nm CMOS IA, relative to conventional current mirror architectures (Xue et al., 3 Jan 2026).

1. Topological Description and Signal Path

The SDCM substitutes the traditional tail device of a current mirror with an NMOS (or PMOS) transistor M3, whose source is connected via a degeneration resistor $R_S$ to the reference node (e.g., ground in NMOS implementations). The reference branch comprises a diode-connected transistor (M3m) and the degeneration resistor, biased with the reference current ($I_{REF}$):

• Reference branch: $I_{REF} \rightarrow$ M3m (diode-connected) $\rightarrow R_S \rightarrow$ GND
• Mirrored branch: M3 (gate = M3m's gate) $\rightarrow R_S \rightarrow$ GND $\rightarrow$ through $R_O$ to the output node

In instrumentation amplifier topologies such as gain-boosted flipped voltage follower (FVF) stages, the SDCM provides the tail-current source with improved noise performance. For PMOS-tail mirrors, all polarities invert ($\text{GND} \leftrightarrow \text{VDD}$), but the functional principle is analogous.

2. Small-Signal Analysis and Transconductance Properties

Analyzing the SDCM in the small-signal domain, with the mirroring device M3 subjected to degeneration via $R_S$, the gate is AC-grounded by the diode-connected reference side. The voltage across the source node $(v_x)$ yields feedback through $I_{REF}$0:

• $I_{REF}$1 (since gate is referenced to ground)
• KCL at $I_{REF}$2 gives: $I_{REF}$3, leading to $I_{REF}$4

The effective transconductance is

$I_{REF}$5

Thus, source degeneration suppresses the device's effective $I_{REF}$6 by roughly $I_{REF}$7.

3. Analytical Characterization: Current Transfer, Output Resistance, and Noise

The SDCM performance metrics can be formalized as follows:

• Current Transfer Ratio:
  • Without degeneration ($I_{REF}$8): $I_{REF}$9 (assuming $I_{REF} \rightarrow$0)
  • With degeneration: $I_{REF} \rightarrow$1
• Output Resistance:
  • Without $I_{REF} \rightarrow$2: $I_{REF} \rightarrow$3
  • With $I_{REF} \rightarrow$4: $I_{REF} \rightarrow$5
• Effective Transconductance:

$I_{REF} \rightarrow$6

• Noise Spectral Density:

The dominant contributors are thermal noise from M3 ($I_{REF} \rightarrow$7) and the resistor ($I_{REF} \rightarrow$8), both suppressed by the loop feedback $I_{REF} \rightarrow$9:

$\rightarrow R_S \rightarrow$0

Input-referred voltage noise:

$\rightarrow R_S \rightarrow$1

Noise Reduction Factor:

$\rightarrow R_S \rightarrow$2

For $\rightarrow R_S \rightarrow$3, $\rightarrow R_S \rightarrow$4, $\rightarrow R_S \rightarrow$5 yields approximately $\rightarrow R_S \rightarrow$6 noise improvement.

4. Trade-Offs: Voltage Headroom and Power Efficiency

Employing source degeneration introduces a design trade-off due to its impact on DC headroom and current transfer:

• Voltage Headroom Penalty: Each resistance value $\rightarrow R_S \rightarrow$7 enforces a DC drop $\rightarrow R_S \rightarrow$8, directly impacting the allocation of available supply voltage, especially in low-voltage designs (e.g. $\rightarrow R_S \rightarrow$9 V). The total headroom impact is $\rightarrow R_S \rightarrow$0.
• Power Consumption: Lower effective $\rightarrow R_S \rightarrow$1 implies reduced closed-loop gain and noise figure at constant current unless $\rightarrow R_S \rightarrow$2 or bias current is adjusted. Practically, $\rightarrow R_S \rightarrow$3 is kept modest, allowing $\rightarrow R_S \rightarrow$4 to remain constant. The noise efficiency factor (NEF) scales as $\rightarrow R_S \rightarrow$5, and a $\rightarrow R_S \rightarrow$6 noise reduction translates to nearly a $\rightarrow R_S \rightarrow$7 current/power reduction under iso-noise conditions; experimentally, a $\rightarrow R_S \rightarrow$8 decrease is reported.

5. CMOS Implementation Guidelines

Effective integration of the SDCM in advanced CMOS processes hinges on device and parameter optimization:

• Degeneration Resistor Selection: $\rightarrow R_S \rightarrow$9 should achieve $\rightarrow$0 for optimal noise/headroom trade-off. In a reference design, $\rightarrow$1 k$\rightarrow$2 at $\rightarrow$3 $\rightarrow$4A yields $\rightarrow$5 mV and $\rightarrow$6 noise reduction.
• Device Sizing:
  • $\rightarrow$7 at minimum (0.25 $\rightarrow$8m) preserves high $\rightarrow$9 and tight headroom constraints for M3m.
  • $R_O$0 in the tens of $R_O$1m range further reduces $R_O$2 at the output, helping recover headroom without affecting output noise PSD (no longer $R_O$3).
• Operational Region: Ensure M3 remains in saturation, i.e., $R_O$4.
• Input Resistance: $R_O$5 is tuned low (4--20 k$R_O$6) so that it controls overall IA noise contribution.

6. Integration in Low-Noise Amplifiers and Empirical Results

SDCMs are integrated as the tail-mirror in FVF-based TC stages within instrumentation amplifiers. Headroom allocation among cascode stacks and gain-boost loops is required, but $R_O$7 mV drop is within budget for $R_O$8 V designs. Positive feedback gain-boosting may be combined to offset reduced loop gain, and dynamic threshold MOSFETs (DTMOS) on the input pair offer orthogonal noise improvement.

Simulations in a 28 nm CMOS IA confirm:

• $R_O$9 noise reduction solely from SDCM; cumulative $\text{GND} \leftrightarrow \text{VDD}$0 reduction with added DTMOS technique.
• $\text{GND} \leftrightarrow \text{VDD}$1 power saving for fixed noise.
• Achieved performance: $\text{GND} \leftrightarrow \text{VDD}$2 V supply voltage, $\text{GND} \leftrightarrow \text{VDD}$3W dissipation, $\text{GND} \leftrightarrow \text{VDD}$4 nV/$\text{GND} \leftrightarrow \text{VDD}$5 input-referred noise, $\text{GND} \leftrightarrow \text{VDD}$6 MHz bandwidth.

7. Design Significance and Application Scope

The source-degenerated current mirror topology efficiently modulates device $\text{GND} \leftrightarrow \text{VDD}$7 and local feedback, providing empirical improvements in input-referred noise and power efficiency at the cost of marginal headroom. Careful selection of $\text{GND} \leftrightarrow \text{VDD}$8 ($\text{GND} \leftrightarrow \text{VDD}$9) and device geometry (wide $R_S$0, minimum $R_S$1) in deep submicron CMOS yields quantifiable noise suppression and energy savings, underscoring SDCM's role as an essential element in cutting-edge IA designs for bioimpedance sensing and related domains (Xue et al., 3 Jan 2026).