Spatio-Temporal Aware Qubit Allocation

• STA Qubit Allocation is a method that assigns logical qubits to physical cores/QPUs by modeling both spatial interconnects and temporal circuit evolution.
• It utilizes deep reinforcement learning and heuristic algorithms like simulated annealing and evolutionary methods to minimize remote gate and teleportation costs.
• The approach integrates into quantum compilation workflows, balancing computational constraints with performance gains and paving the way for multi-objective optimization research.

Spatio-Temporal Aware (STA) qubit allocation is a class of methods developed to assign logical qubits to physical resources (cores or QPUs) in modular and distributed quantum computing architectures, rigorously minimizing communication-induced costs arising from quantum state transfers, remote gate operations, and temporal changes in qubit location. These methods combine explicit modeling of interconnect topology with temporal circuit evolution, leveraging either deep neural architectures or stochastic combinatorial heuristics to enforce physical constraints and optimize for reduced cross-node communication.

1. Formal Problem Definition and Objective Functions

STA qubit allocation precisely formulates the mapping of logical qubits $q \in Q$ over a time-indexed sequence of circuit layers or steps $t = 1,\ldots,T$, assigning each to one of a pool of resources $c \in C$ (multi-core) or $n \in N$ (distributed QPU networks). Decision variables take the form $x_{t,q,c}$ or $x_{q,t} \in \{0,\ldots,N-1\}$.

Key constraints enforced include:

• Exclusive assignment: Each qubit assigned to one core/QPU at each time slice,

$\sum_{c=1}^C x_{t,q,c} = 1\quad\forall q,\, t$

• Capacity: Each core/QPU cannot exceed its maximal occupancy $P_c$ or $C_n$,

$\sum_{q=1}^Q x_{t,q,c} \leq P_c\quad\forall c,\, t$

• Co-location for interacting qubits: For each 2-qubit gate $(g_1,g_2)$ active at slice $t$, these must reside on the same core/QPU,

$\sum_{c=1}^C x_{t,g_1,c} \cdot x_{t,g_2,c} \geq 1$

Objective functions aggregate spatial communication costs and timeline-induced movement:

• For modular architectures, the cost is

$$\text{minimize} \;\;\sum_{t=1}^{T-1} \sum_{q=1}^Q \sum_{s=1}^C \sum_{d=1}^C x_{t,q,s} \cdot x_{t+1,q,d} \cdot D_{s,d}$$

where $D_{s,d}$ models core-to-core transfer cost.

• Distributed architectures extend this with explicit gate and teleportation costs:

$$f(\mathbf{x}) = \underbrace{\sum_{t} \sum_{\mathrm{CX}} \mathrm{dist}(x_{i,t}, x_{j,t})}_{\text{Remote gates}} + \underbrace{\sum_t \sum_q \mathrm{dist}(x_{q,t}, x_{q,t+1})}_{\text{Teleportations}} + \underbrace{\sum_{t,n} g(\#\text{assigned}-C_n)}_\text{Capacity penalty}$$

with $g$ a large additive penalty for violations (Sünkel et al., 15 Jul 2025).

2. Algorithmic Approaches

STA allocation is realized via two principal categories:

A. Deep Reinforcement Learning (DRL)

The DRL method constructs an end-to-end mapping from circuits and hardware graph to core allocations. It employs:

• Input representations: Circuits are partitioned into $T$ time slices; each slice is mapped into an undirected qubit interaction graph. Embeddings are produced via GCNs per slice, aggregated and encoded temporally with a stack of Transformer blocks (multi-head self-attention).
• Spatial encoder: A core-snapshot GCN processes the topology graph $A^{core}$, embedding the current occupancy and available capacity across cores.
• Decoding with attention-based pointer: At each $(t,q)$ step, allocations are made using a cross-attention network, whose output logits are masked to enforce capacity and required co-location for gate participants.
• Rollout and training: Policy optimization proceeds via vanilla REINFORCE, maximizing the negative communication cost (i.e., minimizing actual transfer cost), with reward given only after complete allocations across $T\cdot Q$ steps (Russo et al., 2024).

B. Evolutionary and Simulated Annealing Methods

For distributed settings, schedule-optimization algorithms directly manipulate the assignment matrix $x_{q,t}$:

• Simulated Annealing (SA): Proposes neighbor solutions via single cell/row/column flips and swaps, accepting or rejecting according to the Metropolis criterion with cooling, iterating for $10^5$ steps.
• Evolutionary Algorithm (EA): Maintains a population of assignment schedules or circuit representations, with crossover, mutation, and elitist replacement. EA on the assignment matrix excels for deep circuits (large $T$); a parallel EA can optimize circuit structure itself ("Quantum Circuit Optimization", QCO), especially effective for shallow workloads (Sünkel et al., 15 Jul 2025).

3. Neural Architectures and Input Encoding

The DRL STA model interleaves temporal and spatial structure:

• Temporal encoder: Slices are embedded via GCNs (per-qubit), then pooled and tagged with positional encoding. A Transformer stack produces $T$ slice-level embeddings, encapsulating gate connectivity and allowing cross-slice "lookahead."
• Spatial encoder: Core embeddings include real-time occupancy (max-pooling over assigned qubit embeddings), projected residual capacities, and transfer distances from prior assignments.
• Decoder mechanism: Context vectors for each allocation step fuse global circuit embedding, slice embedding, and per-qubit embedding. Cross-attention over augmented core features yields action probabilities, masked to prohibit infeasible moves.

No explicit tuning between spatial and temporal components is required; the reward inherently induces trade-offs between minimal movement (small hop distances) and packing for future gates.

4. Communication Cost Metrics and Evaluation Protocols

STA allocation methods quantify performance using precisely defined metrics:

• Inter-core or inter-QPU transfer count: The sum of all non-local state movements per circuit execution.
• Remote gate cost: For CX gates operating across boundaries, cost is proportional to physical or graph-theoretic distances.
• Teleportation/relocation cost: Cost is incurred when a logical qubit migrates between cores/QPUs after a time slice.
• Capacity penalties: Schedules over-occupying any core/QPU receive large fixed penalties to enforce feasibility.

Benchmarks include random circuits, standard adders (Cuccaro, Draper), Quantum-Volume circuits, QFT, Graph-State, and small quantum neural networks. Comparative results show DRL-STA and schedule EA methods outperform baseline black-box optimizers by 28–48% on random workloads, with QCO circuit-reshaping methods yielding 48–70% reduction on shallow circuits. Structured circuits (e.g., QFT) may see less reduction if not explicitly incorporated during training (Russo et al., 2024, Sünkel et al., 15 Jul 2025).

5. Integration into Quantum Compilation Workflows

STA allocators are designed for deployment as intermediate mapping passes within distributed- or modular-quantum compiler stacks. The typical pipeline includes:

• Front-end: Circuit is parsed and sliced, timing and gate scheduling determined.
• STA allocation pass: Time-tagged, topology-aware assignments produced, potentially via DRL, EA, or SA as suited to workload profile.
• Back-end: Subcircuits per core/QPU are extracted; remote CX gates and teleportations are annotated with physical network primitives; lower layers manage entanglement distribution and classical control.

Spatio-temporal awareness thus permeates the complete compilation stack, tightly coupling logical-circuit structure and hardware connectivity.

6. Practical Design Guidelines and Trade-offs

Algorithm selection and parametrization should reflect circuit size and network details:

• Shallow/small circuits (Q≤8, depth≤60): Apply QCO for circuit-level optimization, maximizing locality.
• Deep/large circuits (Q≥12, depth≥100): Use schedule-level EA for robust assignment optimization.
• Rapid online allocation: SA provides lower but faster gains.
• Parameter regimes: For EA, $P\approx200$; $G\approx200$; $p_c\approx0.8$, $p_m\approx0.2$; elitism at $10\%$. SA cooling rate $\alpha\approx0.9999$, $T_{min}=10^{-5}$.
• Performance scaling: Evolutionary methods offer highest gains (up to 70%), scaling quadratically in $Q\cdot T$ and requiring runtime in minutes; SA is more lightweight but less effective.

Partitioning circuits into slices with ≤20 gates and combining QCO and EA sequentially is advised. For dynamic environments, SA may offer best adaptivity under fluctuating resources (Sünkel et al., 15 Jul 2025).

7. Future Directions and Research Opportunities

Limitations of current STA allocation methods include:

• Reward functions considering only communication cost; absence of swap operations within cores, dynamic gate durations, heterogeneous core capacities, or evolving link structures.
• Performance degradation on highly regular or structured circuits unless such workloads are included in training sets (for DRL-based models).
• Lack of direct modeling for decoherence or makespan (execution time).

Suggested extensions involve:

• Integrating multi-objective cost functions (communication plus gate/makespan durations).
• Adopting more sample-efficient policy-gradient algorithms (e.g., PPO).
• Enhanced masking for sparse core topologies and improved temporal encoding.
• Training on mixed workloads or applying meta-learning for adaptation.
• Scaling up to hundreds of cores via hierarchical attention or partitioned circuit chunking.
• Full incorporation into quantum compiler pipelines for end-to-end spatio-temporal optimization across heterogeneous distributed quantum platforms (Russo et al., 2024, Sünkel et al., 15 Jul 2025).