SEQC: Stratify-Elaborate Quantum Compiler

• SEQC is a hierarchical, parallelized quantum compiler framework designed for scalable chiplet-based quantum computing.
• It employs a two-stage stratification-elaboration process to partition large circuits into chiplet-local subcircuits, reducing optimization complexity significantly.
• The framework leverages parallelized simulated annealing and SABRE-inspired heuristics to enhance routing fidelity and compile speed by up to 7× compared to traditional methods.

The Stratify-Elaborate Quantum Compiler (SEQC) is a hierarchical, parallelized compilation framework designed for chiplet-based quantum architectures. As the field transitions toward modular quantum devices composed of multiple interconnected chiplets, SEQC addresses the critical scalability challenge posed by heterogeneous inter-chiplet connectivity, highly variable gate fidelities, and the need for efficient cross-chiplet allocation and routing. The compiler decomposes large circuits into chiplet-local subcircuits, compiles them in parallel, and optimizes both for end-to-end fidelity and compilation throughput, establishing itself as an effective strategy for scalable modular quantum computation (Jeng et al., 14 Jan 2025).

1. Hierarchical Pipeline Structure

SEQC divides the compilation process into two distinct stages optimized for chiplet-based hardware:

1. Stratification (one-time per device topology): An input $n$-qubit circuit $\mathcal{C}$ is partitioned into a set of subcircuits $\{\mathcal{C}_1, \ldots, \mathcal{C}_m\}$, each mapped to at most $k$ qubits, where $k$ is the chiplet size. The partition aims to minimize future inter-chiplet communication by grouping densely interacting qubits.
2. Elaboration (per compilation): Each subcircuit $\mathcal{C}_\ell$ is compiled independently onto its assigned chiplet. The process encompasses qubit placement and routing, basis translation into native gate sets, and localized, parallel circuit-level optimizations.

This stratified approach confines high-cost optimization steps to chiplet-local subcircuits, reducing the per-chiplet complexity from $O(n^2)$ to $O(k^2)$, which considerably accelerates compilation for large-scale designs.

2. Qubit Assignment and Partitioning Algorithms

During stratification, SEQC employs a parallelized simulated-annealing heuristic to partition logical qubits into subcircuits:

• Cost Graph Construction: Nodes represent logical qubits; edges connect $(q_i, q_j)$ weighted by the count $w_{i,j}$ of two-qubit gates between them.
• Partition Objective:

$$C_{\rm cut} = \sum_{\substack{i < j\ q_i, q_j\text{ in different blocks}}} w_{i,j}$$

• Multiple independent annealing trials run in parallel. Each annealing step swaps qubits between blocks if it reduces $C_{\rm cut}$. The minimum-cost solution is selected.

Subcircuit-to-chiplet assignment then adapts SABRE-like heuristics for the chiplet supergraph, introducing three classes of SWAP operations: symbiotic (benefits two cross-chiplet edges), commensalistic (helps one without harming others), and parasitic (adverse effect). Candidate layouts are ranked by fidelity-weighted shortest paths, giving preference to high-fidelity, low-latency links between chiplets.

3. Subcircuit Compilation and Optimization

Once mapping is fixed, each subcircuit $\mathcal{C}_\ell$ undergoes an elaboration pipeline:

1. Placement: Selects an injective mapping $$\pi: \{q_0, \ldots, q_{k-1}\} \rightarrow \{Q_0, \ldots, Q_{k-1}\}$$ maximizing an estimated gate fidelity via SABRE-style lookahead:

$$H_{\rm look}(\pi) = \sum_{g\in\text{next }\Delta\text{ gates}}\left[(d_\pi(g)+1) - \alpha\ln f_g\right]$$

1. Routing: For non-adjacent two-qubit gates, inserts a minimal-weight path of SWAPs, with cost per edge $w_e = -\ln f_e + \gamma t_e$, balancing fidelity $f_e$ and latency $t_e$.
2. Basis Translation: Decomposes logical gates to the chiplet’s native gate set using polynomial-time algorithms and caches for small unitaries.
3. Circuit Optimization: Commutation-and-cancellation is applied in parallel within each chiplet subcircuit. Due to strict partitioning, no cross-chiplet optimizations are needed post-stratification.

4. Handling Inter-Chiplet Links

SEQC differentiates between intra-chiplet and inter-chiplet connections, modeling them as distinct edge sets:

• Resource Heterogeneity: Typically, intra-chiplet gates demonstrate higher fidelity ($f_{\rm intra} \gg f_{\rm inter}$) and lower duration ($t_{\rm intra} \ll t_{\rm inter}$).
• Pre-stratification Routing: Gates necessitating cross-chiplet communication are assigned to “halo” qubits at the chiplet periphery to minimize interaction range.
• Immutable Cross-Chiplet SWAPs: Inter-chiplet routes established during stratification remain fixed during elaboration; all subsequent placement/routing cost functions respect the true $f_e$ and $t_e$ values to discourage unnecessary high-cost inter-chiplet operations.

5. Performance Metrics and Experimental Results

SEQC benchmarking utilizes circuits from the Supermarq suite (BitCode, PhaseCode, GHZ, VQE, Hamiltonian-Simulation), scaled up to 1000 qubits. The chiplet model assumes a grid of heavy-hexagon 10-qubit chiplets with the following native parameters: intra-chiplet CZ fidelity 99.4%, duration 34 ns; inter-chiplet SWAP fidelity 89.8%, duration 1400 ns.

Metric	SEQC Result	Comparison
Avg. circuit fidelity gain	+9.3% (up to +49.99%)	Qiskit “peephole” baseline
Avg. compile speedup	$3.27\times$ (max $6.74\times$)	Chiplet-unaware Qiskit
Execution time per shot	$1.92\times$ lower
Stratification cost	$\sim$ baseline single-run	Zero overhead on reuse

A Qiskit 1.2.4 “peephole” routine, modified for chiplet-unaware baseline comparison, introduces SWAPs post hoc, but does not support fidelity- or latency-aware optimization.

6. Parallelization and Scalability

SEQC exploits parallelism at two tiers:

• Stratification stage: Each annealing chain is processed in a separate OS thread/process, yielding a pool of independent solutions.
• Elaboration stage: Subcircuits are mapped and optimized independently, enabling chiplet-level parallel compilation. For $m$ chiplets of size $k\ll n$, this reduces overall complexity from $O(n^2)$ to $mO(k^2)$.
• Resulting speedups are empirically observed between $3\times$ and $7\times$, with elaboration dominating efficiency gains in large circuits.

7. Flexibility and Hyperparameter Tuning

SEQC hyperparameters and objective weights can be tuned for various topologies and device constraints:

• The qubit-to-subcircuit annealer’s schedule and weights are retargetable to accommodate different chiplet numbers and non-uniform or evolving hardware graphs.
• Routing cost weights $$(\lambda_{\mathrm{lat}}, \lambda_{\mathrm{err}}, \gamma)$$ enable balancing between minimal latency and maximum circuit fidelity.
• For exotic modular topologies, including those with nonuniform or routed interconnects, adjusting the edge weights in the physical chiplet graph $G$ is sufficient; the two-stage logic and fidelity-weighted heuristics extend without modification.

The hierarchical separation of stratification and elaboration, along with chiplet-aware routing, enables highly scalable and hardware-optimized compilation that can adapt to the requirements and constraints of next-generation modular quantum devices (Jeng et al., 14 Jan 2025).