Superconductor-Semiconductor Interface Circuits

• Superconductor–semiconductor interface circuits are hybrid systems that merge superconductivity with semiconductor technology, leveraging the proximity effect and Andreev reflection for high transparency and tunable induced gaps.
• They use precise fabrication methods like molecular beam epitaxy and selective area growth to form abrupt, oxide-free interfaces, ensuring reliable device performance in quantum and classical applications.
• These circuits enable state-of-the-art quantum computation, high-speed logic, and reconfigurable elements through gate-tunable Josephson junctions and advanced signal conversion schemes.

Superconductor–semiconductor interface circuits employ the proximity effect, Andreev reflection, and hybrid quantum transport phenomena at engineered S–Sm boundaries to enable circuit functions not attainable in homogeneous materials. These circuits underpin state-of-the-art quantum computation platforms, high-speed logic, SFQ–CMOS interconnects, and reconfigurable circuit elements. The core technical challenge is achieving high interface transparency, reproducible induced superconducting gaps, and scalable lithographic integration, with precise control over critical current, inductance, and noise mechanisms. This article surveys the underlying materials science, interface models, junction designs, amplification and conversion schemes, and emergent application spaces, referencing archetypal device demonstrations.

1. Epitaxial S–Sm Interface Engineering

Monolithic, oxide-free S–Sm interfaces are essential for robust proximity effect and low-dissipation transport. Modern platforms employ molecular beam epitaxy or selective-area growth to produce abrupt, lattice-matched boundaries between III–V semiconductors (InAs, InSb, Ge/SiGe) and conventional (Al) or advanced (Nb, NbTi, TiN, Pb) superconductors. Prototypical systems include:

• Al–InAs/Al–InSb 2DEGs/nanowires: Atomically clean, domain-matched epitaxial interfaces, achieving transmission $\mathcal{T}\gtrsim 0.9$, induced gap $\Delta^* \approx 190$–$200\,\mu$eV, ballistic mean free path $l_e\sim 0.1$–$1\,\mu$m, and gate-tunable supercurrent (Krogstrup et al., 2014, Hertel et al., 2021).
• Nb/NbTi–InAs/Al hybrids: Al interlayer enables metal–metal epitaxy to shallow InAs 2DEG, yielding $\Delta^*\approx1\,$meV, $T_c\sim7$–$10\,$K, and transmission $T>0.9$ (Telkamp et al., 2024).
• Ge/SiGe–Al side-contact structures: Proximitized 2DHG with hard gap $\Delta^*\sim 100\,\mu$eV, strong gate tunability, and $I_cR_N\sim 8\,\mu$V (Vigneau et al., 2018).
• Planar TiN–InAs–Si circuits: High-transparency, sub-1 nm interface roughness, in monolithic SOI-compatible architecture (Ritter et al., 2021).

Domain and lattice matching is quantified via the domain-matching approach: optimal S–Sm combinations minimize strain ($|\delta|\lesssim 1\%$), maximize grain continuity, and avoid amorphous interfacial oxide layers (Krogstrup et al., 2014, Jung et al., 2021). Selective area growth utilizing dielectric masking and in situ superconductor deposition achieves uniformity across wafer scales and supports arbitrary network layouts (Hertel et al., 2021, Jung et al., 2021).

2. S–Sm Josephson Junctions and Gate-Tunable Weak Links

Hybrid Josephson junctions form the principal logic and quantum elements in S–Sm circuits. Gate-defined junctions in 2DEG or nanowire geometries exploit the dependence of carrier density and transmission on gate voltage, resulting in voltage-controlled switching current $I_c(V_g)$. The Andreev bound-state spectrum sets the phase dependence: $$\varepsilon_A(\phi) = \pm\Delta\sqrt{1 - \tau(V_g)\sin^2(\phi/2)}$$ with $\tau(V_g)$ tuned via gate or quantum dot level alignment (Pita-Vidal et al., 29 Dec 2025, Yuan et al., 2021). Short-junction theory (diffusive or ballistic) gives: $$I_c = \frac{\pi\Delta^*}{2eR_N}\tanh\left(\frac{\Delta^*}{2k_BT}\right), \quad I_cR_N \leq 415\,\mu\mathrm{V} \,(\Delta^*\approx190\mu\mathrm{eV})$$ Deviations below theoretical $I_cR_N$ arise from interface scattering, inelastic processes, or imperfect transparency (Hertel et al., 2021, Telkamp et al., 2024).

The induced gap $\Delta^*$ is quantified via NIS tunneling spectroscopy; hard-gap behavior with $G_\mathrm{sg}/G_N \ll 1$ is key for suppressing quasiparticle-induced dissipation in qubits (Kjaergaard et al., 2016, Suominen et al., 2017). Direct evidence for Andreev conductance doubling ($G_\mathrm{ns}=4e^2/h$) in QPCs confirms near-unity transparency and supports low-dissipation interconnects (Kjaergaard et al., 2016). Multiple Andreev reflection features in $I$–$V$ enable extraction of both $\Delta^*$ and interface transparency $\mathcal{T}$ via BTK fits (Hertel et al., 2021, Telkamp et al., 2024).

Table: Representative Parameters for S–Sm JJs

System	$\Delta^*$ ($\mu$eV)	$\mu$ (cm$^2$/Vs)	$I_cR_N$ ($\mu$V)	$\mathcal{T}$
InAs/Al	190–200	$\sim 2\times10^4$	83–300	0.75–1.0
NbTi/Al/InAs	960–1000	$1\times10^5$	200–800	$>$0.9
Ge/SiGe/Al	$\sim 100$	$5\times10^5$	8	high

3. Conversion and Amplification for S–Sm Logic Interfacing

Bridging the SFQ (single flux quantum) and conventional semiconductor (CMOS) signal domains requires specialized interface circuits. Key architectures include:

• JJ-based voltage amplifiers: Suzuki stacks, latching drivers, and SQUID-based pipelines convert SFQ $\sim1\,$mV, ps pulses to tens of mV, ns pulses for CMOS thresholding. Output swing is $n\cdot V_g$, for stacks of $n$ JJs (Mustafa et al., 15 Jan 2026, Razmkhah et al., 2020).
• DC–SQUID transimpedance stages: Nano-SQUID-based preamplifiers provide sub-mV output, $\sim$0.1 Ω output impedance, and nW dissipation for direct coupling to room-temperature comparators (Li et al., 2019).
• Nanocryotrons (nTron): Three-terminal NbN nanowire switches act as current comparators, transforming SFQ pulses (<1 mV) to CMOS-compatible voltages (tens of mV) at GHz rates, with switching energy $<10$ aJ (Zhao et al., 2016).
• Thermal switches: High-impedance WSi nanowire stacks, gated by resistive normal-metal heaters, generate output voltages up to 1.1 V at cryogenic temperatures, directly driving optoelectronics or semiconductor loads (McCaughan et al., 2019).

Best practices include DC biasing to minimize cryostat heat load, maximizing per-channel data rate ($\sim$20–40 Gbps) within available cooling budgets ($<$1 µW/channel at 4 K), and multilevel code conversion (e.g., PAM-4) to optimize data throughput vs. wiring complexity (Mustafa et al., 15 Jan 2026).

4. Circuit Models, Theoretical Descriptions, and Anisotropic Effects

The physics of S–Sm circuits is captured by Bogoliubov–de Gennes or Ginzburg–Landau models extended for hybrid interfaces. Scattering theory (BTK formalism) and Landauer–Büttiker transmission frameworks underpin the microscopic and circuit behavior:

$$G(V) = \frac{2e^2}{h}\sum_n \frac{T_n^2}{(2-T_n)^2} \quad (\mathrm{subgap})$$

Gate-tunable interface transparency allows dynamic control of momentum-filtering and the angular acceptance of Andreev transmission (Breunig et al., 2020).

Hybridization at S–Sm interfaces with strong in-plane mass anisotropy (e.g., BP/Pb) can imprint direction-dependent order parameters on the S layer, yielding angle-dependent gaps $\Delta(\theta)$ and kinetic inductance $L_k(\varphi)$—enabling engineered anisotropic devices and gate-tunable nonlinear resonant elements (Kamlapure et al., 2021).

Equivalent circuit models for S–Sm JJs use a resistively–Andreev–shunted Josephson element (RASJ), combining Josephson inductance, interface Sharvin resistance, and gate-dependent Andreev conductance (Breunig et al., 2020, Hertel et al., 2021).

5. Gate-Tunable Quantum Circuits and Emerging Applications

Voltage-controlled Josephson junctions ("gatemons") enable transistor-free, on-chip-tunable qubits, resonators, and switches. Contemporary implementations include:

• Transmon-like qubits: Replacing the SIS junction with a gate-tunable S–Sm weak link, $E_J(V_g)$ directly modulates qubit frequency, enabling rapid, dissipationless tuning even in magnetic field (Yuan et al., 2021, Pita-Vidal et al., 29 Dec 2025). Achieved frequencies $f_{01}\sim6$–$8\,$GHz with $T_1$ and $T_2$ lifetimes expected to benefit from hard induced gap and high transparency.
• Andreev qubits: Quantum state encoded in the occupation of ABS levels; direct gate control over channel transparency and dot-level position enables access to protected or strongly anharmonic Hamiltonians (Pita-Vidal et al., 29 Dec 2025).
• Majorana-based architectures: Top-down patterned InAs/Al networks support scalable arrays of zero-energy modes, with robust control over network topology, critical for topological quantum computation (Suominen et al., 2017, Jung et al., 2021).

Gate-tunability reduces the circuit footprint relative to flux-based tuning, suppresses magnetic crosstalk, and facilitates 2D integration via standard lithography (Hertel et al., 2021, Ritter et al., 2021). Integration with high-resistivity Si or SOI substrates enables large-scale hybrid logic and quantum system-on-chip approaches (Hertel et al., 2021, Ritter et al., 2021).

6. Scalability, CMOS Compatibility, and Future Directions

Monolithic integration of S–Sm hybrids with Si-based circuits is achieved via selective area growth, Si-compatible superconductors (TiN, NbTiN), and templates allowing arbitrary alignment of nanowires. MOVPE growth and shadow-masking yield scalable, arbitrary networks with atomic interface sharpness, supporting high device yield, reproducibility, and circuit density (Jung et al., 2021, Ritter et al., 2021).

Compatibility with standard CMOS processes—including SOI, ALD dielectrics (HfO$_2$), and flip-chip interconnects—paves the way for fully integrated control/readout infrastructure. Cross-material stacks (Al/Nb, Al/Pb, Pt/Al) further enable operation at elevated $T$ and $B$, supporting environments for advanced qubit modalities and high-bandwidth signal processing (Telkamp et al., 2024, Jung et al., 2021).

Outstanding challenges include further reduction of subgap density-of-states, suppression of two-level system noise at interfaces, integration of inductorless SFQ output drivers, large-signal cryotron improvements, and high-fidelity scaling of gate-controlled quantum modules (Mustafa et al., 15 Jan 2026, Pita-Vidal et al., 29 Dec 2025).

Continuous co-optimization of materials stack, circuit topology, and readout/amplification nodes is expected to drive terabit-scale S–Sm systems toward practical fault-tolerant quantum and classical architectures (Pita-Vidal et al., 29 Dec 2025, Mustafa et al., 15 Jan 2026).