Violaris' Unitary Message-Transfer Primitive

• Violaris' Unitary Message-Transfer Primitive is a quantum-circuit protocol that conditionally transfers classical messages across branches in a coherent, Wigner’s-friend-style setup.
• It uses a fixed sequence of CNOT and Pauli-X gates to implement branch encoding, message writing, copying, and uncomputation, ensuring parallelizable operations and controlled circuit depth.
• Benchmark results across multiple superconducting architectures reveal message pattern-dependent performance, illustrating trade-offs between decoherence, compilers’ routing overhead, and circuit fidelity.

Violaris' Unitary Message-Transfer Primitive (UMP) defines a quantum-circuit protocol for effecting the conditional transfer of a classical message between "branches" in a Wigner's-friend-style circuit under coherent, globally unitary evolution. It provides an operational benchmark for inter-branch communication, with implementations on superconducting quantum hardware spanning up to $n=32$-qubit messages and multi-architecture comparisons. The UMP serves as both a hardware stress-test and a probe of decoherence, circuit compilation efficiency, and device-dependent error sources in near-term quantum processors (Cogburn, 27 Jan 2026, &&&1&&&).

1. Formal Definition and Operator Structure

The UMP is realized in a specific register ordering: $Q$ (the branch/measurement qubit) $\otimes$ $R$ (branch label/reference) $\otimes$ $F$ (friend’s state) $\otimes$ $M \equiv M_1 \ldots M_n$ (n-qubit memory) $\otimes$ $P\equiv P_1\ldots P_n$ (paper/message register). The ideal message-transfer unitary $U_{mt}$ is a fixed composition of CNOT and Pauli-X gates:

$$U_{mt} = U_{swap} \cdot U_{uncompute} \cdot U_{write} \cdot U_{branch} \cdot U_{measure},$$

with:

• $U_{measure} = \mathrm{CNOT}_{Q\rightarrow F}$
• $U_{branch} = \mathrm{CNOT}_{F\rightarrow R}$
• $$U_{write} = \prod_{i=1}^n \mathrm{CNOT}_{F\rightarrow M_i}$$
• $$U_{copy} = \prod_{i=1}^n \mathrm{CNOT}_{M_i\rightarrow P_i}$$
• $$U_{uncompute} = \prod_{i=1}^n \mathrm{CNOT}_{P_i\rightarrow M_i}$$
• $U_{swap} = X_Q \otimes X_R \otimes X_F$

In compact operator form:

$$U_{mt} = (X_Q X_R X_F) \cdot \prod_{i=1}^n \mathrm{CNOT}_{P_i \rightarrow M_i} \cdot \prod_{i=1}^n \mathrm{CNOT}_{M_i \rightarrow P_i} \cdot \mathrm{CNOT}_{F \rightarrow R} \cdot \mathrm{CNOT}_{Q \rightarrow F}$$

This ordering enforces strict sequential logic on message preparation, branch encoding, writing, copying, uncomputation, and final register swaps (Cogburn, 27 Jan 2026).

2. Gate-Level Decomposition and Two-Qubit Depth Scaling

In superconducting-device implementations (e.g., IBM Qiskit backends), the UMP circuit arranges the logical operations for efficient compilation within hardware connectivity constraints. For message size $n$:

• Top three wires: $Q$, $R$, $F$ execute sequential CNOTs and single-qubit $X$ gates.
• Next $n$ wires ($M_1 \ldots M_n$): each receives a CNOT from $F$ (write), a CNOT to $P_i$ (copy), and a reverse CNOT from $P_i$ (uncompute).
• Bottom $n$ wires ($P_1 \ldots P_n$): participate in pairwise (copy/uncompute) CNOTs.

The critical efficiency feature is that the $n$ CNOTs in the copy/uncompute layers commute, supporting full parallelization for those stages. The overall two-qubit gate depth is:

$$\text{depth}_{2Q} = 1 \ (\mathrm{Q}\rightarrow \mathrm{F}) + 1 \ (\mathrm{F}\rightarrow \mathrm{R}) + D_{write} + 1\ (\mathrm{M} \to \mathrm{P\ copy}) + 1\ (\mathrm{P} \to \mathrm{M\ uncompute})$$

where $D_{write}$ is set by the logical-to-physical mapping overhead of fanout from $F$ to the $M_i$ qubits. For message patterns with minimal Hamming weight ("sparse"), $D_{write}=1$, yielding constant-depth circuits. For half-weight and dense patterns, $D_{write}\propto Hamming\ weight$, so depth grows linearly in $n$ (Cogburn, 27 Jan 2026).

3. Message Families and Compilation Cost

The benchmarking campaign distinguishes three message patterns $\mu \in \{0,1\}^n$:

• Sparse (“one-hot”): $\mu = 10\ldots 0$. Only one $M_i$ is flipped; $D_{write}=1$, compiled depth $\approx 5$ (constant).
• Half-weight: Randomly chosen positions, Hamming weight $k=\lfloor n/2 \rfloor$; $D_{write}\sim O(n/2)$, depth $O(n)$.
• Dense (“all-ones”): $\mu = 11\ldots 1$; all $M_i$ active, $D_{write}\sim n$, depth $O(n)$.

On planar superconducting topologies, every non-neighbor CNOT for half/dense families can require SWAP chains, inducing rapidly growing routing overhead. This leads to device- and compiler-seed-dependent variations: transpiler randomness at the coherence-depth frontier becomes a practical limitation for high-weight messages (Cogburn, 27 Jan 2026).

4. Performance Metrics and Diagnostic Observables

Performance evaluation of the UMP is postselected on $R=0$ (the "message-receiver" branch). The key observables are:

• Bitwise success: $$p_{\text{bit}} = (1/n)\sum_{i=1}^{n} \Pr[P_i = \mu_i | R=0]$$
• String success ("all-bits"): $p_{\text{all}} = \Pr[P=\mu | R=0]$
• Memory erasure after uncompute, postselected on $R=1$: $p_{\text{erase}} = \Pr[M=0^n | R=1]$
• Branch contrast $\Delta$ on active bits: for $\mu_i=1$,

$$\Delta = (1/k)\sum_{i:\mu_i=1} [\Pr(P_i=1|R=0) - \Pr(P_i=1|R=1)]$$

• Bitwise mutual information $I(R;P_i)$ (averaged over active bits):

$I(R;P_i) = H(P_i) - H(P_i|R)$

where $H$ is the binary Shannon entropy.

These metrics diagnose both the strict string-level channel performance ($p_{\text{all}}$) and subtler correlations remaining under partial or noisy operation (e.g., $I(R;P_i)$) (Cogburn, 27 Jan 2026).

5. Multi-Architecture Benchmarking Results

Benchmarks were obtained on IBM Eagle (ibm_rensselaer), Nighthawk (ibm_miami), and Heron r2/r3 (ibm_fez, ibm_boston) processors for $n$ up to $32$. No error mitigation was applied; all runs used 4096 shots and Qiskit transpiler level 3. Compilation variability was estimated for half/dense messages using randomized seeds.

Table: Maximum $n$ with $p_{\text{all}}\geq 0.1$ (approximate values):

Backend	Dense	Half	Sparse
ibm_boston	24	32	32
ibm_fez	8	16	32
ibm_miami	16	24	32
ibm_rensselaer	4	8	24

Sparse-family $p_{\text{all}}$ at $n=32$:

• ibm_rensselaer $\approx 0.07$
• ibm_fez $\approx 0.40$
• ibm_miami $\approx 0.52$
• ibm_boston $\approx 0.68$

For half/dense messages, $p_{\text{all}}(n)$ decreases roughly exponentially with $n$, illustrating the compounding effects of SWAP/routing-induced decoherence. A noteworthy result is that, for dense messages at $n=16$, $p_{\text{all}}$ spans from $0.02$ (ibm_rensselaer) to $0.31$ (ibm_boston).

Bitwise mutual information $I(R;P_i)$ remains nonzero for dense messages even when $p_{\text{all}}\to 0$ at large $n$, signifying that some branch–message correlation persists despite an overall loss of string fidelity (Cogburn, 27 Jan 2026).

6. Hardware Noise, Error Sources, and Transpiler Variability

• Sparse family: Due to constant two-qubit depth ($\approx 5$), this regime serves as a controlled probe of device-dependent noise; hardware-to-hardware variability in $p_{\text{all}}$ at $n=32$ primarily reflects differences in intrinsic decoherence and CNOT fidelity.
• Half/dense families: Main limitation is SWAP/routing overhead. As the logical depth increases with message Hamming weight, both device connectivity and randomness in transpiler optimization yield large variations in circuit depth and $p_{\text{all}}$. Close to the coherence frontier, compiler-seed fluctuations can induce order-unity swings in success probability (Cogburn, 27 Jan 2026).

7. Amplitude Sweep, Divergence (“Cousins”) Sweep, and Channel Constraints

The UMP supports protocol-level stress tests probing channel linearity and complexity dependence:

• Amplitude sweep (no amplification test): By preparing $Q$ to set $\Pr(R=0)=p_0$ and running $U_{mt}$, one obtains $\Pr(R=0)_{final} \approx 1 - p_0$. Empirically, the measured marginal weights perfectly track the ideal $1-p_0$ relation across all tested backends, indicating no spurious amplification (Cogburn, 27 Jan 2026).
• Cousins-divergence sweep: A 16-qubit friend state is prepared with Hamming distance $d$ between branches, adding $d$ $X$-gates to $U_{swap}$. At fixed $n=16$, sweeping $d$ from $0$ to $16$, the branch contrast $\Delta$ falls linearly with $d$, reflecting increased circuit depth and cumulative noise.
• Channel constraints: In five-qubit (minimal) protocols, additional performance witnesses are defined:
  • Visibility $V = |\Pr(R=0|P=1) - \Pr(R=1|P=1)|$, extracted from $Z$-basis readout.
  • Coherence witnesses $W_X$, $W_Y$: multi-qubit parities in $X$ and $Y$ bases, sensitive to off-diagonal coherence.
  • Phase-sensitive magnitude $C_{mag} = \sqrt{W_X^2 + W_Y^2}$.

Benchmarks on ibm_fez ($20,000$ shots) yield $V_{hw} = 0.877 \pm 0.0034$, $W_X = 0.840 \pm 0.0038$, $W_Y = -0.811 \pm 0.0041$, $C_{mag} = 1.167 \pm 0.0040$, compared to ideal $C_{mag} = 1.414$. Visibility is primarily sensitive to population, while $W_X, W_Y$ are directly attenuated by modeled dephasing channels: for $W_X = 0.8398$, a dephasing strength $\lambda_{est} \approx 0.08$ explains the observed reduction, setting the device constraint on coherence preservation (Altman, 22 Jan 2026).

• M. Violaris, “Quantum observers can communicate across multiverse branches,” (Violaris, 13 Jan 2026) (2026).
• C. V. Cogburn, "Inter-branch message transfer on superconducting quantum processors: a multi-architecture benchmark," (Cogburn, 27 Jan 2026) (2026).
• C. V. Cogburn, "Wigner's Friend as a Circuit: Inter-Branch Communication Witness Benchmarks on Superconducting Quantum Hardware," (Altman, 22 Jan 2026) (2026).