Automatic hardware routing and switch-update code generation for WSE stencil communications

Develop automatic code generation of hardware routing configurations and dynamic switching updates for stencil communication patterns on the Cerebras Wafer-Scale Engine, including star-shaped stencil patterns, so that routing and switch control can be produced by the compiler rather than relying on software-based routing patterns or manual configuration.

Background

The paper introduces a compiler pipeline that lowers stencil computations to CSL for the Cerebras Wafer-Scale Engine (WSE), with communication managed by a CSL-based runtime library. While the library supports star-shaped stencils and chunked communication using tasks, it currently relies on preconfigured software-level routing and does not generate hardware routing configurations or dynamic switch updates.

The authors note complementary work that provides software-based routing patterns, but emphasize that compiler-generated hardware routing and switching control is not yet available—even for stencil-specific cases—highlighting a gap needed to fully automate and optimize communication on the WSE fabric.