Shape optimization of superconducting transmon qubit for low surface dielectric loss

Abstract: Surface dielectric loss of superconducting transmon qubit is believed as one of the dominant sources of decoherence. Reducing surface dielectric loss of superconducting qubit is known to be a great challenge for achieving high quality factor and a long relaxation time ($T_{1}$). Changing the geometry of capacitor pads and junction wire of transmon qubit makes it possible to engineer the surface dielectric loss. In this paper, we present the shape optimization approach for reducing Surface dielectric loss in transmon qubit. The capacitor pad and junction wire of the transmon qubit are shaped as spline curves and optimized through the combination of the finite-element method and global optimization algorithm. Then, we compared the surface participation ratio, which represents the portion of electric energy stored in each dielectric layer and proportional to two-level system (TLS) loss, of optimized structure and existing geometries to show the effectiveness of our approach. The result suggests that the participation ratio of capacitor pad, and junction wire can be reduced by 16% and 26% compared to previous designs through shape optimization, while overall footprint and anharmonicity maintain acceptable value. As a result, the TLS-limited quality factor and corresponding $T_{1}$ were increased by approximately 21.6%.

• The paper shows that optimized capacitor pad geometries can reduce metal-substrate participation ratios by 15-18%, leading to a 21.6% improvement in qubit quality factor.
• The study employs the DIRECT algorithm and Ansys HFSS simulations to iteratively refine spline shapes while maintaining practical design constraints.
• The optimized designs extend the transverse relaxation time (T1) to approximately 86.5 μs, indicating a significant advancement toward scalable quantum computing.

Shape Optimization of Superconducting Transmon Qubits

Introduction

The study investigates the reduction of surface dielectric loss in superconducting transmon qubits through shape optimization, focusing primarily on enhancing the transverse relaxation time ($T_1$). Surface dielectric loss is a primary factor limiting the quality factor of qubits, rendering it a significant challenge in superconducting quantum processor design. The paper details how modifications to the capacitance pad and the junction wire, through spline geometry and optimization algorithms, can dramatically decrease participation ratios, hence reducing dielectric loss without significantly impacting the qubit's operational footprint.

Surface Participation Ratio Calculation

Superconducting transmon qubits suffer from decoherence primarily due to parasitic two-level system (TLS) defects at interfaces—metal-air (MA), metal-substrate (MS), and substrate-air (SA). Participatory modeling quantifies this by evaluating the electric field’s contribution to loss in these regions. The paper uses a combination of analytical approximation and numerical simulation to compute the participation ratios of these dielectric layers effectively. The electrostatic model employed, which eschews complex field divergence at the metal edges, uses scaling factors derived from conformal mapping techniques and numerical methods to approximate localized fields and participation accurately.

Optimization Method

The optimization leverages the DIRECT algorithm—an adaptive global optimization method well-suited to high-dimensional design spaces which are computationally expensive. The objective function targets the minimization of the MS participation ratio in the capacitor pad's interior region, justified by demonstrating a correlative reduction in perimeter participation. The optimization framework, implemented using Ansys HFSS, incorporates constraints on junction wire length and pad footprint to maintain manufacturability and practical dimensions. Spline shapes characterize the capacitor pads, and the optimization algorithm iteratively refines these shapes to converge on minimal loss configurations.

Results and Discussion

The optimized designs were evaluated through electromagnetic simulations, indicating a significant reduction in surface participation ratios. Specifically, the optimized configuration exhibited a 15-18% decrease in total participation ratios compared to conventional double-pad geometries. This reduction translates to a 21.6% increase in the TLS-limited quality factor and corresponding $T_1$, reaching values of approximately 2.72 million and 86.5 $\mu$s, respectively. The geometric adjustments adhere to practical constraints, particularly in tapering the junction wire to minimize participation without increasing the qubit footprint—showcasing a strategic compromise between size and performance.

Conclusion

This research successfully correlates shape optimization with improved transmon qubit performance by reducing surface dielectric losses via geometric alterations. These results substantiate the potential of employing sophisticated design tools common in electromagnetic systems within quantum device engineering. Future studies could extend these principles to incorporate novel materials or address other decoherence sources like quasiparticle losses. Integrating these optimized designs in coherent qubit structures could facilitate advancements in error rates, thus progress towards scalable, fault-tolerant quantum computation.