All-Nitride ALD Qubits

• All-nitride ALD qubits are superconducting circuits where both electrodes and tunnel barriers are made from nitrides deposited with atomic precision.
• The process enables precise control over barrier thickness and tunable critical current densities spanning seven orders of magnitude for robust performance.
• Scalable, CMOS-compatible fabrication reduces TLS losses and supports high-performance qubits operating above 300 mK using high-Tc materials like NbN and TiN.

All-nitride atomic-layer-deposition (ALD) qubits are a class of superconducting quantum circuits in which every key layer—including both electrodes and the tunnel barrier—comprises epitaxial or amorphous nitrides, with films deposited using plasma-enhanced ALD to achieve atomically sharp interfaces and sub-nanometer thickness control. In recent implementations, such as NbN/AlN/NbN trilayer transmon architectures, the ALD technique enables scalable, CMOS-compatible fabrication with critical-current densities tuned over seven decades and coherence times retained into elevated temperature regimes (>300 mK). All-nitride ALD qubits leverage the high superconducting critical temperature ($T_c$) and stability of nitrides (e.g., NbN, TiN) for robust performance, minimal two-level-system (TLS) loss, and adaptability to integration with foundry processes (Wang et al., 12 Nov 2025, Shearrow et al., 2018).

1. Atomic-Layer Deposition of All-Nitride Josephson Junctions

All-nitride ALD qubits are predicated on the conformal, cycle-based ALD process, which enables precise, uniform growth of NbN/AlN/NbN trilayer junctions. The process employs an Ultratech/Cambridge Fiji G2 plasma-enhanced ALD reactor operating at 300–400 °C, with substrate options including c-plane sapphire (for optical alignment) or Si (for CMOS compatibility). The process sequence involves:

• NbN: tert-butylimido tris(diethylamido)niobium (TBTDEN) precursor, Ar carrier.
• AlN: trimethylaluminum (TMA) precursor, Ar carrier.
• N$_2$/H$_2$ plasma (1:1 flow, 300 W RF) for nitridation and surface activation.
• Each ALD cycle: metal precursor pulse (0.5–1 s), Ar purge (10–20 s), N$_2$/H$_2$ plasma exposure (5 s), and a final Ar purge (10–20 s).
• Trilayer geometry: bottom (25–50 nm) and top (25–50 nm) NbN films sandwiching AlN barrier layers ranging from approximately 0.5 nm to 3 nm (set by 5–40 TMA cycles, $a ≈ 0.076$ nm/cycle).
• At each NbN/AlN interface, an additional 10 plasma-only cycles are used to optimize interface sharpness and reduce residual ligands.

Cross-sectional STEM analysis reveals atomically abrupt interfaces and uniform AlN barriers (e.g., 1.6 nm at 21 cycles), while atom-probe tomography confirms oxygen impurities under 5% and barrier thickness variations less than 5% in a 15 nm lateral domain. Large-scale junction arrays (100–1000 devices) exhibit consistent room-temperature resistance-area relations, implying excellent film uniformity.

2. Barrier Thickness Calibration and Critical Current Density Tuning

The number of ALD cycles controls the AlN barrier thickness $d$ according to $d ≃ a N$ with $a ≈ 0.076$ nm/cycle (e.g., 21 cycles yields $d ≈ 1.6$ nm). This parameter directly tunes the Josephson junction critical current density ($J_c$):

$\log_{10} J_c~(\mathrm{A/cm^2}) = -0.34~N + 4.2$

$J_c(N) ≃ 10^{4.2}·10^{-0.34 N}~\mathrm{A/cm^2}$

or, substituting for $N = d/a$:

$$J_c(d) ≃ J_0 \exp(-\alpha d),~\text{with}~\alpha ≃ (0.34\,\ln 10)/a ≃ 3.3~\mathrm{nm}^{-1}$$

This formalism allows $J_c$ to be tuned from approximately $10^3$ A/cm$^2$ ($N \sim 5$ cycles) down to $10^{-4}$ A/cm$^2$ ($N \sim 30$ cycles), spanning seven orders of magnitude. The resulting junction resistance-area products ($R_n A$) are stable near $20.8$ k$\Omega\cdot\mu$m$^2$ across batches.

3. Josephson Junction and Qubit Electrical Properties

ALD qubits exhibit device-level and qubit-level electrical properties consistent with high-quality Josephson junctions:

• 4 K DC $I$–$V$ characteristics: gap voltages $V_g ≈ 4.2$ mV (implying $\Delta ≈ 2.1$ meV; $T_c$(NbN) ≈ 13 K), subgap-to-normal resistance ratio $R_{sg}/R_n$ up to $\approx 55$.
• Switching current ($I_{sw}$) analysis supports $J_c$ extraction via $I_c = (\pi/4) I_g$ (where $I_g$ is gap current), with $J_c = I_c / A$ ($A = \pi D^2/4$ for a circular junction).
• Josephson ($E_J$) and charging ($E_C$) energies,
  • $E_J = \Phi_0 I_c/(2\pi)$, $\Phi_0 = h/2e$
  • $E_C = e^2/(2C_\Sigma)$, with $C_\Sigma$ the total capacitance including the junction and shunt pads,
• Transmon transition frequencies ($f_{01}$) calculated as $f_{01} \approx [\sqrt{8E_J E_C} - E_C]/h$ (approximating [Koch et al., 2007]), but extracted numerically (e.g., $α/2π ≈ 223$ MHz anharmonicity).

4. Transmon Integration, Device Geometry, and Coherence Measurements

The all-nitride ALD junctions are integrated into transmon qubits using a flip-chip platform:

• Q-chip (top): ALD trilayer, Josephson junction and Ti/Au bonding pads.
• C-chip (bottom): NbN readout resonator, feedline, and Ti/Au pads.
• Flip-chip process utilizes room-temperature gold–gold bonding with sub-5μm alignment.

Qubit capacitance is set via large shunt pads on both chips, with total energy participation $p_J = C_J / C_\Sigma$ in the range 0.2–0.8. Readout employs quarter-wave resonators with $f_c ≈ 6$–7 GHz, qubit–resonator coupling rates $g/2π ≈ 50$–70 MHz, and measured readout internal quality factors $Q_i ≈ (2–6)\times10^4$ at the single-photon level.

Measured qubit parameters at base temperature (10 mK) are summarized:

Qubit	D$_J$ (μm)	$p_J$	$f_q$ (GHz)	$E_J/h$ (GHz)	$E_C/h$ (GHz)	$g/2\pi$ (MHz)	$T_1$ (μs)	$T_2^*$ (μs)
A1	1.0	0.30	5.063	20.02	0.172	48.7	1.43±0.03	0.74±0.04
A2	0.8	0.20	4.089	11.79	0.196	67.5	2.87±0.07	0.65±0.04
A3	0.8	0.20	4.057	11.55	0.197	68.5	3.00±0.03	1.20±0.04
B1	2.0	0.75	3.983	11.98	0.182	49.0	2.66±0.05	0.69±0.04
B2	2.0	0.74	3.907	11.19	0.188	55.0	3.43±0.08	–

Key time-domain results include Rabi oscillations with $\Omega_R/2\pi ≈ 18$ MHz, energy relaxation times ($T_1$) from $1.4$ μs to $3.4$ μs (mean $T_1 ≈ 3.0$ μs for A3), and Ramsey dephasing times ($T_2^*$) of $0.65$–$1.2$ μs. Notably, microsecond-scale $T_1$ persists up to $T = 400$ mK, where $T_1$ decreases gradually according to a spin-boson model: $T_1(T) ∝ [1 + \coth({\hbar ω_q}/{2k_B T})]^{-1}$.

5. Elevated-Temperature Performance Enabled by High-$T_c$ Nitrides

The NbN electrodes ($T_c ≈ 13$ K; $\Delta ≈ 2.1$ meV) enable coherent qubit operation well above the temperatures accessible to conventional Al-based qubits. At $T > 300$ mK ($k_BT ≈ 26$ μeV), the density of thermally-generated quasiparticles $n_{qp} ∝ \exp(-\Delta / k_B T)$ remains negligible, ensuring that $T_1$ remains in the sub-microsecond to microsecond regime at $T=310$–$400$ mK. This represents a significant relaxation of cryogenic cooling requirements in quantum processors, contrasting with Al-based circuits, where $T_1$ rapidly degrades above $\sim200$ mK.

6. Process Scalability, Foundry Integration, and Loss Mechanisms

ALD processes provide wafer-scale, conformal deposition with angstrom-level thickness controllability, directly translating to $J_c$-spread below 5% across 100 mm wafers. The approach is compatible with CMOS back-end and photolithography techniques suitable for 0.8 μm junctions and below (193 nm immersion). Flip-chip architectures separate the qubit and wiring optimizations, avoid lossy sidewall spacers, reduce TLS participation by eliminating amorphous AlO$_x$, and use a PECVD-free backend.

Intrinsic losses are subordinate to extrinsic packaging and surface oxides, with current loss analyses showing:

• Subgap conduction-limited $Q_{JJ}>5\times 10^5$
• Gold-bond loss $Q_{Au}>3\times 10^6$
• AlN piezo loss $Q>10^5$
• Qubit quality factors $Q_q = 4$–$9\times 10^4$

This suggests that the ALD nitride stack and flip-chip process do not fundamentally limit coherence; rather, further improvement is expected as foundry process integration and surface-passivating strategies mature.

7. All-Nitride ALD Qubits in Context: Comparison and Future Prospects

Titanium nitride (TiN) grown by ALD further extends all-nitride strategies to quantum resonators and kinetic inductors, with demonstrated sheet kinetic inductance $L_s$ up to $234$ pH/□ (for $t=8.9$ nm), internal quality factors $Q_i ≈ 0.4$–$1.0$ million for $t \geq 14$ nm, and characteristic impedances $Z_c$ up to 28 kΩ (Shearrow et al., 2018). In hybrid and protected qubit applications, these properties increase photon-qubit/spin coupling by a factor of 24 compared to 50 Ω architectures. Limitations from surface oxides and TLSs, along with etch and substrate treatments, remain key optimization areas.

A plausible implication is that all-nitride ALD techniques, encompassing both NbN/AlN and TiN nanoscale films, define a technological basis for scalable, high-coherence qubits compatible with elevated temperature operation and industrial foundry practices, providing routes to large-scale quantum processors with relaxed cryogenic requirements and robust materials engineering.