All-Nitride ALD Qubits

• All-nitride ALD qubits are superconducting circuits where both electrodes and tunnel barriers are made from nitrides deposited with atomic precision.
• The process enables precise control over barrier thickness and tunable critical current densities spanning seven orders of magnitude for robust performance.
• Scalable, CMOS-compatible fabrication reduces TLS losses and supports high-performance qubits operating above 300 mK using high-Tc materials like NbN and TiN.

All-nitride atomic-layer-deposition (ALD) qubits are a class of superconducting quantum circuits in which every key layer—including both electrodes and the tunnel barrier—comprises epitaxial or amorphous nitrides, with films deposited using plasma-enhanced ALD to achieve atomically sharp interfaces and sub-nanometer thickness control. In recent implementations, such as NbN/AlN/NbN trilayer transmon architectures, the ALD technique enables scalable, CMOS-compatible fabrication with critical-current densities tuned over seven decades and coherence times retained into elevated temperature regimes (>300 mK). All-nitride ALD qubits leverage the high superconducting critical temperature ($T_c$) and stability of nitrides (e.g., NbN, TiN) for robust performance, minimal two-level-system (TLS) loss, and adaptability to integration with foundry processes (Wang et al., 12 Nov 2025, Shearrow et al., 2018).

1. Atomic-Layer Deposition of All-Nitride Josephson Junctions

All-nitride ALD qubits are predicated on the conformal, cycle-based ALD process, which enables precise, uniform growth of NbN/AlN/NbN trilayer junctions. The process employs an Ultratech/Cambridge Fiji G2 plasma-enhanced ALD reactor operating at 300–400 °C, with substrate options including c-plane sapphire (for optical alignment) or Si (for CMOS compatibility). The process sequence involves:

• NbN: tert-butylimido tris(diethylamido)niobium (TBTDEN) precursor, Ar carrier.
• AlN: trimethylaluminum (TMA) precursor, Ar carrier.
• N$_2$/H$_2$ plasma (1:1 flow, 300 W RF) for nitridation and surface activation.
• Each ALD cycle: metal precursor pulse (0.5–1 s), Ar purge (10–20 s), N$_2$/H$_2$ plasma exposure (5 s), and a final Ar purge (10–20 s).
• Trilayer geometry: bottom (25–50 nm) and top (25–50 nm) NbN films sandwiching AlN barrier layers ranging from approximately 0.5 nm to 3 nm (set by 5–40 TMA cycles, $a ≈ 0.076$ nm/cycle).
• At each NbN/AlN interface, an additional 10 plasma-only cycles are used to optimize interface sharpness and reduce residual ligands.

Cross-sectional STEM analysis reveals atomically abrupt interfaces and uniform AlN barriers (e.g., 1.6 nm at 21 cycles), while atom-probe tomography confirms oxygen impurities under 5% and barrier thickness variations less than 5% in a 15 nm lateral domain. Large-scale junction arrays (100–1000 devices) exhibit consistent room-temperature resistance-area relations, implying excellent film uniformity.

2. Barrier Thickness Calibration and Critical Current Density Tuning

The number of ALD cycles controls the AlN barrier thickness $d$ according to $d ≃ a N$ with $a ≈ 0.076$ nm/cycle (e.g., 21 cycles yields $d ≈ 1.6$ nm). This parameter directly tunes the Josephson junction critical current density ($_2$0):

$_2$1

$_2$2

or, substituting for $_2$3:

$_2$4

This formalism allows $_2$5 to be tuned from approximately $_2$6 A/cm$_2$7 ($_2$8 cycles) down to $_2$9 A/cm$_2$0 ($_2$1 cycles), spanning seven orders of magnitude. The resulting junction resistance-area products ($_2$2) are stable near $_2$3 k$_2$4m$_2$5 across batches.

3. Josephson Junction and Qubit Electrical Properties

ALD qubits exhibit device-level and qubit-level electrical properties consistent with high-quality Josephson junctions:

• 4 K DC $_2$6–$_2$7 characteristics: gap voltages $_2$8 mV (implying $_2$9 meV; $_2$0(NbN) ≈ 13 K), subgap-to-normal resistance ratio $_2$1 up to $_2$2.
• Switching current ($_2$3) analysis supports $_2$4 extraction via $_2$5 (where $_2$6 is gap current), with $_2$7 ($_2$8 for a circular junction).
• Josephson ($_2$9) and charging ($_2$0) energies,
  • $_2$1, $_2$2
  • $_2$3, with $_2$4 the total capacitance including the junction and shunt pads,
• Transmon transition frequencies ($_2$5) calculated as $_2$6 (approximating [Koch et al., 2007]), but extracted numerically (e.g., $_2$7 MHz anharmonicity).

4. Transmon Integration, Device Geometry, and Coherence Measurements

The all-nitride ALD junctions are integrated into transmon qubits using a flip-chip platform:

• Q-chip (top): ALD trilayer, Josephson junction and Ti/Au bonding pads.
• C-chip (bottom): NbN readout resonator, feedline, and Ti/Au pads.
• Flip-chip process utilizes room-temperature gold–gold bonding with sub-5μm alignment.

Qubit capacitance is set via large shunt pads on both chips, with total energy participation $_2$8 in the range 0.2–0.8. Readout employs quarter-wave resonators with $_2$9–7 GHz, qubit–resonator coupling rates $a ≈ 0.076$0–70 MHz, and measured readout internal quality factors $a ≈ 0.076$1 at the single-photon level.

Measured qubit parameters at base temperature (10 mK) are summarized:

Qubit	D$a ≈ 0.076$2 (μm)	$a ≈ 0.076$3	$a ≈ 0.076$4 (GHz)	$a ≈ 0.076$5 (GHz)	$a ≈ 0.076$6 (GHz)	$a ≈ 0.076$7 (MHz)	$a ≈ 0.076$8 (μs)	$a ≈ 0.076$9 (μs)
A1	1.0	0.30	5.063	20.02	0.172	48.7	1.43±0.03	0.74±0.04
A2	0.8	0.20	4.089	11.79	0.196	67.5	2.87±0.07	0.65±0.04
A3	0.8	0.20	4.057	11.55	0.197	68.5	3.00±0.03	1.20±0.04
B1	2.0	0.75	3.983	11.98	0.182	49.0	2.66±0.05	0.69±0.04
B2	2.0	0.74	3.907	11.19	0.188	55.0	3.43±0.08	–

Key time-domain results include Rabi oscillations with $d$0 MHz, energy relaxation times ($d$1) from $d$2 μs to $d$3 μs (mean $d$4 μs for A3), and Ramsey dephasing times ($d$5) of $d$6–$d$7 μs. Notably, microsecond-scale $d$8 persists up to $d$9 mK, where $d ≃ a N$0 decreases gradually according to a spin-boson model: $d ≃ a N$1.

5. Elevated-Temperature Performance Enabled by High-$d ≃ a N$2 Nitrides

The NbN electrodes ($d ≃ a N$3 K; $d ≃ a N$4 meV) enable coherent qubit operation well above the temperatures accessible to conventional Al-based qubits. At $d ≃ a N$5 mK ($d ≃ a N$6 μeV), the density of thermally-generated quasiparticles $d ≃ a N$7 remains negligible, ensuring that $d ≃ a N$8 remains in the sub-microsecond to microsecond regime at $d ≃ a N$9–$a ≈ 0.076$0 mK. This represents a significant relaxation of cryogenic cooling requirements in quantum processors, contrasting with Al-based circuits, where $a ≈ 0.076$1 rapidly degrades above $a ≈ 0.076$2 mK.

6. Process Scalability, Foundry Integration, and Loss Mechanisms

ALD processes provide wafer-scale, conformal deposition with angstrom-level thickness controllability, directly translating to $a ≈ 0.076$3-spread below 5% across 100 mm wafers. The approach is compatible with CMOS back-end and photolithography techniques suitable for 0.8 μm junctions and below (193 nm immersion). Flip-chip architectures separate the qubit and wiring optimizations, avoid lossy sidewall spacers, reduce TLS participation by eliminating amorphous AlO$a ≈ 0.076$4, and use a PECVD-free backend.

Intrinsic losses are subordinate to extrinsic packaging and surface oxides, with current loss analyses showing:

• Subgap conduction-limited $a ≈ 0.076$5
• Gold-bond loss $a ≈ 0.076$6
• AlN piezo loss $a ≈ 0.076$7
• Qubit quality factors $a ≈ 0.076$8–$a ≈ 0.076$9

This suggests that the ALD nitride stack and flip-chip process do not fundamentally limit coherence; rather, further improvement is expected as foundry process integration and surface-passivating strategies mature.

7. All-Nitride ALD Qubits in Context: Comparison and Future Prospects

Titanium nitride (TiN) grown by ALD further extends all-nitride strategies to quantum resonators and kinetic inductors, with demonstrated sheet kinetic inductance $d ≈ 1.6$0 up to $d ≈ 1.6$1 pH/□ (for $d ≈ 1.6$2 nm), internal quality factors $d ≈ 1.6$3–$d ≈ 1.6$4 million for $d ≈ 1.6$5 nm, and characteristic impedances $d ≈ 1.6$6 up to 28 kΩ (Shearrow et al., 2018). In hybrid and protected qubit applications, these properties increase photon-qubit/spin coupling by a factor of 24 compared to 50 Ω architectures. Limitations from surface oxides and TLSs, along with etch and substrate treatments, remain key optimization areas.

A plausible implication is that all-nitride ALD techniques, encompassing both NbN/AlN and TiN nanoscale films, define a technological basis for scalable, high-coherence qubits compatible with elevated temperature operation and industrial foundry practices, providing routes to large-scale quantum processors with relaxed cryogenic requirements and robust materials engineering.