Merged-Element Transmons

• Merged-element transmons are superconducting qubits that leverage the Josephson junction's intrinsic capacitance to replace large, lossy shunt capacitors, reducing decoherence from parasitic two-level systems.
• Their design confines over 90% of the electromagnetic energy to the tunnel barrier, resulting in significant footprint reduction and more uniform qubit frequency allocation.
• Advanced fabrication methods, including Al/AlOₓ, FinMET, and geometric inductor integration, enable tunable nonlinearity and fast two-qubit interactions in scalable quantum circuits.

A merged-element transmon (MET) is a superconducting qubit in which the Josephson junction’s intrinsic self-capacitance replaces the large, lossy planar shunt capacitor traditional to the transmon architecture. The MET’s electromagnetic energy is almost entirely confined to the tunnel barrier region, suppressing decoherence mechanisms associated with parasitic two-level systems (TLS) at other circuit interfaces and enabling substantial footprint reduction, tighter qubit–frequency allocation, and simplified fabrication compatible with modern semiconductor processing. METs can be realized using micrometer-scale Al/AlOₓ/Al junctions, epitaxial Al/Si/Al structures (“FinMET”), or amorphous-trilayer junctions, and are now extended to include designs utilizing explicit geometric inductors for tunable nonlinearity and fast two-qubit interactions.

1. Circuit Architecture and Physical Principles

The canonical MET consists of a single micrometer-scale Josephson junction (JJ) fabricated from Al/AlOₓ/Al or similar superconductor–insulator–superconductor trilayers, engineered so that both the Josephson nonlinearity and the transmon’s shunt capacitance $C_{\text{tot}}$ arise from the junction itself. Whereas conventional transmons use large ($\gtrsim 10^4\,\mu\text{m}^2$) coplanar/interdigitated capacitors to provide $C_{\text{shunt}}$ (and thus drive the qubit into the charge-insensitive regime with $E_J/E_C \sim 20$–$100$), METs leverage the fact that for a barrier thickness $d \sim 2$–$10$ nm and area $A \sim 1$–$5\,\mu\text{m}^2$, the junction capacitance $C_{JJ} = \varepsilon_0 \varepsilon_r A / d$ ($\gtrsim 10^4\,\mu\text{m}^2$0 for AlOₓ, $\gtrsim 10^4\,\mu\text{m}^2$1 for Si barriers) naturally yields the $\gtrsim 10^4\,\mu\text{m}^2$2–$\gtrsim 10^4\,\mu\text{m}^2$3 fF range required for transmon operation (Mamin et al., 2021, Goswami et al., 2021, Daum et al., 26 Sep 2025).

A representative MET circuit contains:

• A single Josephson junction shunted only by its intrinsic capacitance;
• Optional “antenna” arms for capacitive coupling to resonators;
• In some variants, a geometric inductor $\gtrsim 10^4\,\mu\text{m}^2$4 for additional spectral tunability and sideband coupling (Fasciati et al., 2024).

In all embodiments, the electromagnetic energy participation ratio $\gtrsim 10^4\,\mu\text{m}^2$5 exceeds $\gtrsim 10^4\,\mu\text{m}^2$6, concentrating the electric field in the junction barrier. This configuration minimizes field overlap with surface dielectrics and interface defects that are known to dominate loss in large-area conventional transmons (Mamin et al., 2021, Daum et al., 26 Sep 2025).

2. Fabrication Modalities and Materials Interfaces

METs have been demonstrated using a variety of barrier materials and processing approaches:

• Al/AlOₓ/Al junctions: Standard shadow-evaporation with long O₂ oxidations yields barriers of $\gtrsim 10^4\,\mu\text{m}^2$72 nm and areas $\gtrsim 10^4\,\mu\text{m}^2$81.4–2.4 $\gtrsim 10^4\,\mu\text{m}^2$9m$C_{\text{shunt}}$0, with $C_{\text{shunt}}$1 nA and $C_{\text{shunt}}$2 fF (Mamin et al., 2021). Annealing (5 min, $C_{\text{shunt}}$3–$C_{\text{shunt}}$4C) raises the oxide gap and junction resistance, correlating with improved device quality factors.
• In-situ bandaged Dolan process for Al JJs: Two-junction SQUID loops (“mergemon” qubits) with double oxidation and a thin tuning layer provide reproducible barrier thickness $C_{\text{shunt}}$5–$C_{\text{shunt}}$6 nm. Device footprints are minimized by compact islands with reduced geometric capacitance (Daum et al., 26 Sep 2025).
• Si FinMET: Fin-based Si(110) substrates, anisotropically etched to expose atomically flat Si{111} planes, serve as intrinsic crystalline barriers. Epitaxial Al is deposited on the fin sidewalls, forming Al/Si/Al junctions with target barrier thickness $C_{\text{shunt}}$7–$C_{\text{shunt}}$8 nm. Collective capacitances $C_{\text{shunt}}$9–2 fF/$E_J/E_C \sim 20$0m are achieved, and process flow is compatible with standard CMOS fabrication (Goswami et al., 2021).
• Nb/a-Si/Nb trilayers: Used in early MET demonstrations, these devices replace the coplanar shunt with an amorphous Si barrier (thickness $E_J/E_C \sim 20$19 nm, area $E_J/E_C \sim 20$2m), although dielectric loss remains higher in amorphous layers (Zhao et al., 2020).
• Geometric inductor integration: A simple geometric inductor in parallel with the JJ enables flux-tunable anharmonicity and rapid two-qubit gates while maintaining a single-JJ, low-participation layout (Fasciati et al., 2024).

For Si-based METs, Schottky barrier heights and interface atomic relaxations fundamentally determine tunneling characteristics. First-principles calculations for Al(111)/Si(111) and CoSi$E_J/E_C \sim 20$3(111)/Si(111) structures yield $E_J/E_C \sim 20$4-type barriers $E_J/E_C \sim 20$5–$E_J/E_C \sim 20$6 eV; the optimal regime for 4–5 GHz multi-qubit operation is obtained for $E_J/E_C \sim 20$7–8 nm crystalline Si with $E_J/E_C \sim 20$8–0.6 eV, specifically the CoSi$E_J/E_C \sim 20$9(111)-Si(111) B8 interface (Nangoi et al., 2024).

3. Electromagnetic Energy Distribution and Loss Participation

The MET is engineered to confine nearly all ($100$090%) of its electric field energy within the tunnel barrier, quantified by the participation ratio

$100$1

while geometric and substrate/vacuum participations are suppressed ($100$2–$100$3 fF added by antenna arms or leads) (Mamin et al., 2021, Daum et al., 26 Sep 2025).

By contrast, conventional planar transmons exhibit $100$4 (most energy in the coplanar shunt capacitor). This design choice in the MET minimizes the impact of dielectric loss from substrate and surface oxides, as confirmed by measured substrate-vacuum participation rates ($100$5nm$100$6 in METs vs $100$7nm$100$8 in coplanar transmons) (Mamin et al., 2021).

Loss analysis using participation ratios and extracted loss tangents (from TLS spectroscopy under strain and electric fields) shows that once surface EPR is minimized, junction TLS become the dominant decoherence channel. Measured and simulated loss tangents are

• $100$9–$d \sim 2$0 (surface)
• $d \sim 2$1 (junction, from TLS density and coupling)
• $d \sim 2$2 in the best annealed AlOₓ devices (Mamin et al., 2021, Daum et al., 26 Sep 2025).

Participation ratios for Si-based barriers (FinMET) are expected to be lower due to the absence of amorphous oxides and use of atomically flat interfaces (Goswami et al., 2021, Nangoi et al., 2024).

4. Energy Spectra, Spectroscopy, and Qubit Performance

In the weakly anharmonic (transmon) limit, the MET Hamiltonian retains its canonical form:

$d \sim 2$3

with $d \sim 2$4 and $d \sim 2$5. The spectrum is characterized by transition frequencies

$d \sim 2$6

and anharmonicity $d \sim 2$7.

• Al/AlOₓ METs: $d \sim 2$8–$d \sim 2$9 (unannealed), $10$0–$10$1 (annealed), $10$2–$10$3, $10$4–$10$5 (Mamin et al., 2021).
• Mergemons (Al JJ SQUIDs): $10$6–$10$7, $10$8–$10$9, $A \sim 1$0–$A \sim 1$1, tunable via external flux (Daum et al., 26 Sep 2025).
• Nb/a-Si/Nb: $A \sim 1$2, $A \sim 1$3, $A \sim 1$4 (Zhao et al., 2020).
• FinMET: Tuning achieved by adjusting Si fin thickness on the nanometer scale; predicted $A \sim 1$5, $A \sim 1$6–$A \sim 1$7s (Goswami et al., 2021).

Qubit coherence times and quality factors strongly depend on design and processing:

• Al/AlOₓ MET, annealed: median $A \sim 1$8s, with some devices achieving $A \sim 1$9s and $5\,\mu\text{m}^2$0 (Mamin et al., 2021).
• Mergemon (Approach B): $5\,\mu\text{m}^2$1 up to $5\,\mu\text{m}^2$2s ($5\,\mu\text{m}^2$3); Approach A: $5\,\mu\text{m}^2$4–$5\,\mu\text{m}^2$5s (Daum et al., 26 Sep 2025).
• Nb/a-Si/Nb: $5\,\mu\text{m}^2$6 ns, $5\,\mu\text{m}^2$7 ns, limited by a-Si loss (Zhao et al., 2020).
• FinMET: Resonators with Q up to $5\,\mu\text{m}^2$8 pre-thinning; post-thinning and surface cleaning projected to reach $5\,\mu\text{m}^2$9 and $C_{JJ} = \varepsilon_0 \varepsilon_r A / d$0 (Goswami et al., 2021).

Frequency uniformity across dies is improved in mergemon designs due to insensitivity to lithographic area fluctuations; measured $C_{JJ} = \varepsilon_0 \varepsilon_r A / d$1 for $C_{JJ} = \varepsilon_0 \varepsilon_r A / d$2 (Daum et al., 26 Sep 2025).

5. Loss Mechanisms, Coherence, and Two-Level Systems

The MET paradigm is motivated by the desire to concentrate effort on controlling a single, relatively well-defined interface: the tunnel barrier. In conventional transmons, decoherence is dominated by parasitic TLS at the edges of coplanar shunt capacitors and junction leads. In METs and mergemons, the dominant loss mechanisms are:

• Surface TLS: Amorphous layers at metal–air and substrate–air interfaces. Their contribution is minimized by careful design (enlarged islands, narrowed leads, optimized layout) that reduces the electric participation ratio (EPR) of these surfaces. Approach B in mergemon qubits achieves $C_{JJ} = \varepsilon_0 \varepsilon_r A / d$3 and a ten-fold reduction in surface TLS density compared to conventional designs (Daum et al., 26 Sep 2025).
• Junction TLS: Intrinsic to the tunnel barrier (AlOₓ or a-Si), with higher densities in thicker or amorphous barriers. Junction TLS exhibit strong coupling to the qubit due to high local $C_{JJ} = \varepsilon_0 \varepsilon_r A / d$4-field, with volume densities $C_{JJ} = \varepsilon_0 \varepsilon_r A / d$5–$C_{JJ} = \varepsilon_0 \varepsilon_r A / d$6GHz$C_{JJ} = \varepsilon_0 \varepsilon_r A / d$7m$C_{JJ} = \varepsilon_0 \varepsilon_r A / d$8 for AlOₓ barriers. The measured loss tangent $C_{JJ} = \varepsilon_0 \varepsilon_r A / d$9 can become the limiting factor after surface loss suppression (Daum et al., 26 Sep 2025).
• Fabrication dependence: Double oxidation, annealing, and advanced surface treatments reduce both surface and junction TLS. Prospective strategies include crystalline or epitaxial barriers and thermal/alternating-bias annealing (Daum et al., 26 Sep 2025, Mamin et al., 2021).
• Geometric inductor METs: Coherence metrics (single-qubit $\gtrsim 10^4\,\mu\text{m}^2$00s, $\gtrsim 10^4\,\mu\text{m}^2$01s) are comparable to conventional transmons; the key advance lies in the suppression of correlated ZZ errors and in gate performance (Fasciati et al., 2024).

Table: Comparison of Coherence Metrics

MET Variant	Median $\gtrsim 10^4\,\mu\text{m}^2$02 ($\gtrsim 10^4\,\mu\text{m}^2$03s)	Best $\gtrsim 10^4\,\mu\text{m}^2$04 ($\gtrsim 10^4\,\mu\text{m}^2$05s)	$\gtrsim 10^4\,\mu\text{m}^2$06 (max)
Al/AlOₓ/Al (annealed)	46	>200	$\gtrsim 10^4\,\mu\text{m}^2$07
Al/AlOₓ/Al (unannealed)	13	34	$\gtrsim 10^4\,\mu\text{m}^2$08
Mergemon (Approach B)	39–131	130	$\gtrsim 10^4\,\mu\text{m}^2$09
Nb/a-Si/Nb	0.055	—	—
FinMET (projected, post-thin)	100–300	—	>$\gtrsim 10^4\,\mu\text{m}^2$10

6. Design Scaling, Implementation Trade-offs, and Integration

METs offer orders-of-magnitude footprint reduction. A planar MET junction area is $\gtrsim 10^4\,\mu\text{m}^2$11–$\gtrsim 10^4\,\mu\text{m}^2$12m$\gtrsim 10^4\,\mu\text{m}^2$13, compared to $\gtrsim 10^4\,\mu\text{m}^2$14m$\gtrsim 10^4\,\mu\text{m}^2$15 for a typical planar shunt capacitor, affording packing densities $\gtrsim 10^4\,\mu\text{m}^2$16 qubits/cm$\gtrsim 10^4\,\mu\text{m}^2$17 (Mamin et al., 2021, Goswami et al., 2021, Zhao et al., 2020). In FinMETs, integration leverages mature CMOS fin-processing, with all steps—mask deposition, anisotropic KOH etch, digital (atomic-layer) thinning, and shadow metal deposition—fully compatible with large-scale foundry environments (Goswami et al., 2021). The merged-element layout allows elimination of radiative “antenna” modes, reduction of inter-qubit crosstalk, and more uniform wiring.

For silicon-interface METs, first-principles studies (Nangoi et al., 2024) indicate that interface configuration and barrier thickness/schottky-barrier height trade-offs directly set $\gtrsim 10^4\,\mu\text{m}^2$18 and thus $\gtrsim 10^4\,\mu\text{m}^2$19. The Josephson current density scales as $\gtrsim 10^4\,\mu\text{m}^2$20 with $\gtrsim 10^4\,\mu\text{m}^2$21; for target frequencies 4–5 GHz, design rules require crystalline Si barriers of $\gtrsim 10^4\,\mu\text{m}^2$22–8 nm and $\gtrsim 10^4\,\mu\text{m}^2$23–$\gtrsim 10^4\,\mu\text{m}^2$24 eV. The optimal structures, such as CoSi$\gtrsim 10^4\,\mu\text{m}^2$25(111)/Si(111) in the B8 configuration, have both favorable energetics and a suitable tunneling barrier to reproducibly achieve desired $\gtrsim 10^4\,\mu\text{m}^2$26 (Nangoi et al., 2024).

7. Extensions: Enhanced Circuit Topologies and Gate Operations

Recent variations extend the MET architecture by integrating parallel Josephson junction arrays (NMon) or explicit shunt inductors (inductively shunted transmon, IST).

• NMon: By replacing a single JJ with parallel N and M-junction arrays, tunable through external flux, the NMon achieves enhanced relative anharmonicity $\gtrsim 10^4\,\mu\text{m}^2$27–$\gtrsim 10^4\,\mu\text{m}^2$28 while preserving transmon-like charge and flux matrix elements. Such designs offer additional suppression of flux-noise-induced dephasing (scaling $\gtrsim 10^4\,\mu\text{m}^2$29), with smooth interpolation between transmon and fluxonium modalities (Can et al., 2024).
• IST (Inductively Shunted Transmon): Integration of a geometric $\gtrsim 10^4\,\mu\text{m}^2$30 enables flux-tunable anharmonicity (the sign of $\gtrsim 10^4\,\mu\text{m}^2$31 can cross zero), passive cancellation of static ZZ errors in two-qubit circuits, and rapid first-order sideband gates ($\gtrsim 10^4\,\mu\text{m}^2$3275–125 ns) with up to $\gtrsim 10^4\,\mu\text{m}^2$33 in experiment. The simplicity and passive ZZ protection are promising for 2D qubit lattices with large native gate sets (Fasciati et al., 2024).

These advancements demonstrate that MET paradigms are compatible with qubit tileability, aggressive scaling, and advanced control protocols, while offering insight into the fundamental materials challenges limiting further improvement.

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References:

(Mamin et al., 2021, Goswami et al., 2021, Fasciati et al., 2024, Daum et al., 26 Sep 2025, Zhao et al., 2020, Can et al., 2024, Nangoi et al., 2024)