CMOS-Compatible On-Chip RIS

• CMOS-compatible on-chip RIS are monolithic electromagnetic surfaces that integrate VO₂-based switching for programmable beam steering at millimeter-wave frequencies.
• The design employs binary phase shifting with a 60×60 dense array to achieve a 180° phase span and low insertion loss (~1 dB) around 100 GHz.
• CMOS fabrication enables co-integration with RF/mm-wave components, offering scalable, agile beamforming for emerging 6G on-chip wireless interconnects.

A CMOS-compatible on-chip Reconfigurable Intelligent Surface (RIS) is a monolithic electromagnetic structure engineered within a standard microfabrication flow for dynamic manipulation of millimeter-wave and sub-THz propagating fields. Integrating switchable elements into silicon die layouts, these RIS platforms target key functionalities—particularly programmable beam steering—crucial for emerging 6G wireless interconnects. The approach leverages the interoperability of advanced thin films, such as VO₂, with back-end-of-line processes on silicon foundries, enabling co-integration with RF/mm-wave transceivers and digital control circuitry. The core mechanism is realized via binary or multi-bit reconfigurable phase-shifting unit cells, arrayed densely to form high-gain, agile apertures. The recently demonstrated 100-GHz CMOS-compatible RIS achieves efficient π-switchable reflection phase, low insertion loss (~1 dB), and array-level beamforming with practical prototype validation (Su et al., 21 Dec 2025).

1. Unit Cell Design and Electromagnetic Operation

The elemental RIS unit cell is a multilayer stack on high-resistivity Si substrate (thickness $h_\mathrm{si}=300$ µm), comprising (bottom to top): sputtered Cu ground, a 15 µm plasma-enhanced CVD SiO₂ dielectric, Cu meandered delay-line ($w_\mathrm{d}=30$ µm, $\ell_\mathrm{d}=400$ µm), a VO₂ phase-change patch ($30$ µm length bridging the delay line), and a top-illuminated slot resonator ($w_\mathrm{s}=187.5$ µm, $\ell_\mathrm{s}=562.5$ µm, pitch $p=1.125$ mm).

Parameter	Value
$W_\mathrm{sub}$	1.125 mm
$h_\mathrm{si}$	300 µm
$h_\mathrm{SiO_2}$	15 µm
$w_\mathrm{s}$	187.5 µm
$\ell_\mathrm{s}$	562.5 µm
$w_\mathrm{d}$	30 µm
$\ell_\mathrm{d}$	400 µm

Capacitive coupling from incident waves energizes the delay-line. VO₂, with a sharp conductivity transition ($\sigma > 10^5$ S/m ON, $\sigma < 10^0$ S/m OFF, $T_\mathrm{c} \sim 68^\circ$C), toggles the phase delay: in the ON state, current traverses $\ell_\mathrm{d}$ only; in OFF, a detour ($\Delta\ell \sim 200$ µm) inserts an additional delay, yielding $\approx \pi$ phase shift at $f_0=100.75$ GHz.

Reflection coefficient at the slot is:

$$\Gamma(f) = \frac{Z_\mathrm{unit}(f) - Z_0}{Z_\mathrm{unit}(f) + Z_0}$$

where $Z_0 = 377\,\Omega$,

with $$Z_\mathrm{unit}(f) \approx jZ_\mathrm{line} \tan[\beta(f)\,\ell_\mathrm{eff}]$$ for $\ell_\mathrm{eff} = \ell_\mathrm{d}$ (ON) or $\ell_\mathrm{d} + \Delta\ell$ (OFF).

Simulated and measured results confirm a 180° phase span with reflection loss $\leq 1.2$ dB (99–102.5 GHz):

$f$ (GHz)	$\phi_\mathrm{ON}/\phi_\mathrm{OFF}$ (sim, deg)	$|S_{11}|_\mathrm{ON/OFF}$ (sim, dB)	$\phi_\mathrm{ON}$ (meas, deg)	$\phi_\mathrm{OFF}$ (meas, deg)
99.75	–90 / +90	–1.1 / –1.0	–85 / +95	+100 / –80
100.75	0 / 180	–1.0 / –1.1	+5 / 185	+182 / +4
101.75	+90 / +270	–1.2 / –1.2	+92 / +272	+275 / +90

2. Array Architecture and Beamforming Principles

A $60 \times 60$ array of the described unit cell achieves a total aperture of $67.5 \times 67.5$ mm² (pitch $p=1.125$ mm $\sim 0.375\lambda_0$ at 100.75 GHz). VO₂ heating and digital control lines are routed to each cell in the SiO₂ layer.

Beam steering is governed by the array factor:

$$\mathrm{AF}(\theta, \phi) = \sum_{m=1}^M \sum_{n=1}^N \exp\left(j \left[ k d ( m \sin\theta\cos\phi + n \sin\theta\sin\phi ) + \phi_{mn} \right] \right)$$

where $\phi_{mn} \in \{0, \pi\}$ corresponds to each VO₂-tuned phase state.

Simulated boresight directivity is $25.1$ dBi (beamwidth $1.8^\circ$). Measured gains:

Scan Ang. ($\theta_\mathrm{scan}$)	Peak Gain (dBi)	Sidelobe Level (dB)
$0^\circ$	24.4	–13
$\pm15^\circ$	23.8	n.a.
$\pm30^\circ$	22.5	n.a.

Beamforming flexibility is limited to binary (1-bit) quantization, enabling mainlobe steering but constraining sidelobe suppression.

3. CMOS-compatible Fabrication Workflow

The process leverages standard microelectronics and back-end-of-line-compatible steps:

1. Sputter deposit 200 nm Cu on 300 µm high-resistivity Si (ground).
2. Photolithography and lift-off for Cu delay-line metallization.
3. PECVD SiO₂ (15 µm); pattern lithographically; etch vias.
4. VO₂ deposition by sputtering or ALD in gaps; lift-off; anneal ($\sim 350^\circ$C).
5. Top Cu slot structure by lithography/sputter/lift-off.
6. Optional final passivation (SiO₂ or polymer).

Photomicrographs confirm die-scale pattern fidelity and element regularity for the $60 \times 60$ array.

4. Experimental Validation and Comparative Performance

Measured ON/OFF reflection contrast at boresight is $27.1$ dB; contrast exceeds $20$ dB throughout 98–103 GHz. Single-cell $|S_{11}| \approx -1.0$ dB indicates a per-cell efficiency of $\sim 79\%$; full aperture efficiency $\sim 65\%$, accounting for element quantization and edge taper. VO₂ switching energy is $<50$ nJ/cell; thermal cycling yields configuration shifts within $50$ ns. Continuous wave power handling per cell reaches $\sim 100$ mW, limited by VO₂ heat dissipation.

Selected comparative data:

Reference	$f_0$ (GHz)	Loss (dB)	Phase bits	CMOS compatible
(Su et al., 21 Dec 2025)	100.75	1.0	1	Yes
Machado 2024	28	0.8	1	No (PCB)
Gros 2021	28	2.5	1	No (MSS)
Xu 2025 (liquid crystal)	300	3.2	1	No

A plausible implication is that the presented loss and integration characteristics are superior in the 100 GHz regime among known RIS technologies.

5. Impact for On-Chip Wireless and 6G Applications

Full CMOS/microfabrication compatibility enables co-packaging with transceiver front-ends, such as VCOs and mixers, for on-chip, beam-steerable 100 GHz wireless links. VO₂ thermal management—via microheater topology and substrate thermal vias—mitigates heat accumulation and accelerates switching. Controllable arrays can be managed via scalable CMOS row/column decoders and embedded SRAM, supporting $<100$ µs configuration time for $60 \times 60$ elements.

Advanced applications are contingent on finer pitch ($<0.5$ mm) and tighter overlay for higher frequencies (200–300 GHz). Possible future directions include multi-bit phase quantization (via cascaded VO₂ sections), hybrid amplitude/phase modulation for sidelobe suppression, and sub-ns response RIS through alternative switches (e.g., fast-doped VO₂, graphene).

6. Outlook and Research Directions

CMOS-compatible on-chip RIS constitute a foundational hardware platform for 6G sub-THz dynamic beam steering. The established prototype achieves $\pi$ phase shift, low transmission loss, and practical array-level agility at $100.75$ GHz, validated by both full-wave simulation and measurement (Su et al., 21 Dec 2025). Scaling of phase resolution, switching speed, and integration with digital control are key axes for future work. The demonstrated performance establishes a benchmark for high-density, low-loss, reconfigurable surfaces compatible with silicon microelectronics, supporting the broader agenda of dense, programmable, wireless on-chip interconnects for next-generation information processing.