On-chip Reconfigurable Intelligent Surfaces (RIS)

• On-chip RIS is a CMOS-compatible metasurface that imparts programmable 1-bit phase shifts to electromagnetic waves, essential for 6G wireless links.
• The device uses VO₂-based switches to achieve a 180° phase difference with low loss and rapid switching times around 50 ns at 100 GHz.
• Integrated in a 60×60 cell array, it demonstrated ~79% reflection efficiency with measured peak gains near 24.4 dBi and agile beam steering capabilities.

A CMOS-compatible on-chip reconfigurable intelligent surface (RIS) is a planar, electrically controlled metasurface device, fully compatible with CMOS fabrication flows, designed to impart programmable phase shifts to incident electromagnetic waves. Realized at 100 GHz, such RIS-on-chip systems exploit layered, lithographically defined structures incorporating switchable conductive oxides—here vanadium dioxide (VO₂)—to enable rapid, binary (1-bit) phase control with low loss and high system-level integration. These platforms are foundational for 6G sub-terahertz wireless communication, supporting monolithic beam steering within compact, CMOS-integrable form factors (Su et al., 21 Dec 2025).

1. Unit-Cell Architecture and Electromagnetic Behavior

Each RIS unit cell consists of a hierarchical stack on high-resistivity silicon, enabling both CMOS compatibility and low-loss reconfigurability. The cross-sectional hierarchy is air → slot resonator → SiO₂ isolation layer → patterned Cu delay-line with integrated VO₂ patch → continuous Cu ground plane → Si substrate. Dimensional parameters are listed in Table 1.

Parameter	Value
W_sub	1.125 mm
h_si	300 µm
h_sio₂	15 µm
w_s	187.5 µm
ℓ_s	562.5 µm
w_d	30 µm
ℓ_d	400 µm

The slot capacitively couples incident plane waves into the delay-line, with the VO₂ patch bridging a 30 µm gap. In the ON state (T > $T_c \approx 68 \,\mathrm{^\circ C}$), VO₂ exhibits $\sigma \approx 10^5$ S/m and shorts the meander, resulting in overall effective line length $\ell_{\text{eff}} = \ell_d$. In the OFF (insulating) state, $\sigma < 10^0$ S/m, and current detours an additional $\Delta \ell \approx 200\,µ$m, producing a differential electrical phase of approximately $\pi$ radians ($180^\circ$) at the design frequency $f_0 = 100.75$ GHz. The reflection coefficient at the slot port, deembedded to the reference plane, is given by

$$\Gamma(f) = \frac{Z_{\text{unit}}(f) - Z_0}{Z_{\text{unit}}(f) + Z_0},$$

with $Z_0 = 377\,\Omega$ and $\sigma \approx 10^5$0 where $\sigma \approx 10^5$1 toggles between the two current paths. Full-wave HFSS simulations confirm a reflection magnitude $\sigma \approx 10^5$2 dB in both states, with a simulated and measured phase difference of $\sigma \approx 10^5$3 at $\sigma \approx 10^5$4 over a bandwidth of $\sigma \approx 10^5$5 GHz (Su et al., 21 Dec 2025).

2. Array-Level Synthesis and Beam Steering

The RIS comprises a $\sigma \approx 10^5$6 unit-cell array (3,600 cells), with planar cell pitch $\sigma \approx 10^5$7 mm ($\sigma \approx 10^5$8 at 100.75 GHz), forming a $\sigma \approx 10^5$9 aperture. VO₂ heating lines and control buses are confined within the SiO₂ interlayer to minimize parasitics and enable rapid addressability.

Beamforming is governed by the planar array factor: $\ell_{\text{eff}} = \ell_d$0 where $\ell_{\text{eff}} = \ell_d$1 encodes the RIS cell binary phase state via VO₂ heating. Quantized phase patterns—implemented via programmable VO₂ states—steer the main lobe to arbitrary $\ell_{\text{eff}} = \ell_d$2 angles per reflectarray synthesis conventions. Simulated boresight directivity reaches $\ell_{\text{eff}} = \ell_d$3 dBi, with measured peak gain at $\ell_{\text{eff}} = \ell_d$4 of $\ell_{\text{eff}} = \ell_d$5 dBi and half-power beamwidth of $\ell_{\text{eff}} = \ell_d$6. Sidelobe suppression approaches $\ell_{\text{eff}} = \ell_d$7 dB, with scan-range peak gain variation within $\ell_{\text{eff}} = \ell_d$8 dB up to $\ell_{\text{eff}} = \ell_d$9 (Su et al., 21 Dec 2025).

3. CMOS-Compatible Microfabrication

Fabrication adheres strictly to established CMOS and silicon micromachining protocols, ensuring full system-on-chip integration viability. The sequential process is as follows:

1. High-resistivity silicon wafer ($\sigma < 10^0$0m) is coated with $\sigma < 10^0$1nm sputtered Cu for the ground plane.
2. Photolithographic definition and lift-off patterning of the delay-line Cu.
3. $\sigma < 10^0$2m SiO₂ deposition via PECVD; lithographically patterned and selectively etched for via formation.
4. VO₂ is deposited (sputtering or ALD) exclusively within the delay-line gap, patterned by lift-off and annealed at ~350$\sigma < 10^0$3C to ensure stoichiometry.
5. Topside slot Cu deposition by lithography/sputtering/lift-off.
6. Optional encapsulation with thin SiO₂ or polymer for environmental passivation.

Optical micrographs confirm high yield and sub-micron overlay tolerances across both the $\sigma < 10^0$4 and reduced $\sigma < 10^0$5 test arrays (Su et al., 21 Dec 2025).

4. Experimental Characterization and Performance Benchmarking

At normal incidence ($\sigma < 10^0$6), ON/OFF reflection contrast exceeds $\sigma < 10^0$7 dB at $\sigma < 10^0$8, remaining above $\sigma < 10^0$9 dB over an operational range of $\Delta \ell \approx 200\,µ$0–$\Delta \ell \approx 200\,µ$1 GHz. Single cell $\Delta \ell \approx 200\,µ$2 is measured at about $\Delta \ell \approx 200\,µ$3 dB, implying $\Delta \ell \approx 200\,µ$4 reflection efficiency. Overall array aperture efficiency, accounting for edge taper and quantization loss, is $\Delta \ell \approx 200\,µ$5.

VO₂ switching is thermally actuated with pulse energies $\Delta \ell \approx 200\,µ$6 nJ per cell and switching times near $\Delta \ell \approx 200\,µ$7 ns; per-cell CW power handling is limited by VO₂ dissipation ($\Delta \ell \approx 200\,µ$8 mW). Table 2 below summarizes comparative performance with recent RIS approaches.

Reference	$\Delta \ell \approx 200\,µ$9 (GHz)	Loss (dB)	Phase Resolution	CMOS Compat.
(Su et al., 21 Dec 2025)	100.75	1.0	1-bit	Yes
Machado 2024	28	0.8	1-bit	No (PCB)
Gros 2021	28	2.5	1-bit	No (MSS)
Xu 2025 (liq. crystal)	300	3.2	1-bit	No

The CMOS-compatible on-chip RIS achieves state-of-the-art loss and phase tunability at 100 GHz, with unique scalability benefits and integration capabilities (Su et al., 21 Dec 2025).

5. Implications and Prospects for 6G Wireless Integration

Monolithic integration of the presented RIS with on-chip transceivers (e.g., VCOs, mixers) enables beam-steerable wireless links targeting 6G sub-terahertz networking. Control is managed by a CMOS decoder and SRAM architecture, reconfiguring all 3,600 cells in $\pi$0 μs aggregate time. The principal limitations are VO₂ array thermal management and the scale-dependent reduction of cell pitch and overlay accuracy at frequencies beyond 200 GHz.

Prominent future directions include:

• Multi-bit phase quantization via cascaded VO₂ or alternative materials, increasing angular steering resolution.
• Hybrid amplitude/phase control metasurfaces for improved sidelobe suppression and beam shaping.
• Adoption of sub-nanosecond switch technologies (fast-doped VO₂ or graphene-integrated switches).
• Optimization of thermal vias and micro-heater layouts to minimize switching latency and substrate heating under high duty-cycle operation.

A plausible implication is that such CMOS-compatible RIS devices, offering low loss, sub-wavelength pitch, and fully electronic addressability, will become foundational blocks in dense, high-frequency 6G chip-to-chip wireless interconnects and agile communication front-ends (Su et al., 21 Dec 2025).