Excitonic Circuits

• Excitonic circuits are integrated systems that manipulate charge-neutral excitons and related quasiparticles, enabling ultrafast and low-loss signal processing.
• They employ nanoscale architectures such as vertical heterojunctions, coupled quantum wells, and 2D material stacks to achieve tunable logic gating and efficient routing.
• By combining electrical and optical controls, these circuits offer scalable platforms for hybrid quantum–photonic integration and next-generation optoelectronic devices.

Excitonic circuits are integrated structures that exploit the charge-neutral, bosonic nature of excitons and their related quasiparticles (trions, polaritons) as carriers of information or energy. These circuits utilize the propagation, manipulation, and detection of excitons within carefully tailored nanoscale architectures, with potential for ultrafast optoelectronic signal processing, low-loss interconnects, and hybrid quantum–photonic platforms leveraging semiconductor, molecular, or engineered material systems.

1. Fundamental Exciton and Trion Physics

Excitons are Coulomb-bound electron–hole pairs in a semiconductor or insulator, exhibiting neutral charge, distinct spin and valley degrees of freedom, and single- or multi-particle interactions. Neutral excitons ($X^{0}$) do not carry net charge and thus cannot generate a dc photocurrent under drift. By contrast, trions ($X^{-}$ or $X^{+}$), being charged three-particle bound states, enable direct charge-current generation under appropriate conditions. Negative trions in WS$_2$ are bound by $E_b = E_{X^0}-E_{X^-}$ with typical $E_b=20$–$40$ meV at room temperature.

Resonant optical excitation at the trion transition energy can prepare valley-coherent trions, whose flow is tunable via external parameters (electric fields, doping, interlayer coupling), underpinning ultrafast excitonic switching. Exciton–exciton dipolar interactions further provide nonlinearities crucial for device operation and logic gating, while the valley and spinor structure of exciton–polaritons enables encoding and manipulation of additional quantum information (Das et al., 2020).

2. Device Architectures and Material Platforms

A multitude of architectures have been realized for excitonic circuits:

• Vertical heterojunction trion switches employ FLG / WS$_2$ / MLG stacks on Si/SiO$_2$ with built-in vertical fields and gate-tunable WS$_2$ bandgap, supporting sub-100 fs charge–current switching via valley-resolved trion resonance (Das et al., 2020).
• Electrostatic routing of interlayer excitons utilizes naturally stacked WSe$_2$ bilayers, encapsulated in hBN, and graphene gates to sculpt 2D potential landscapes with field-programmable traps, anti-channels and programmable routers (Liu et al., 2019).
• Optically patterned coupled quantum wells (GaAs/AlGaAs) form crossed-ramp or flat-energy channels, implementing all-optical excitonic transistors and routers with high on/off contrast based on dipolar indirect excitons (Andreakou et al., 2013).
• Exciton–polariton logic circuits in GaAs/AlAs microcavities with laterally defined potential wells and 1D channels realize bistable spinor gates (AND, NOT) with ballistic spin precession (Espinosa-Ortega et al., 2013).
• MoSe$_2$–WSe$_2$ potential slides create unidirectional channels and all-optical gating using patterned FLG gates, exploiting the drift of IXs in electrostatically defined gradients (Shanks et al., 2022).
• Photonic integrated chips (PICs) with 2D TMDC heterobilayers on Si$_3$N$_4$ microresonators harness near-field coupling of interlayer excitons to whispering gallery modes, achieving valley-selective routing and Purcell-enhanced emission (Mandal et al., 2022).

Such platforms support both free-propagating (“wire”) and localized (“node”) excitonic states, with circuit elements interconnected via optical, electrical, or excitonic coupling.

3. Signal Routing, Logic, and Gating Mechanisms

Excitonic circuits achieve logic and switching via:

• Gate-tunable resonance: In trion switches, $V_g$ modulates the trion transition $E_T(V_g)=E_{X^0}-E_b+\Delta E(V_g)$, enabling gate voltage or spectral tuning of the on/off state, with ON/OFF current ratios up to $\sim$10 (Das et al., 2020).
• All-optical gating: Crossed-ramp transistors employ optically created gate excitons to locally modify energy barriers via dipole–dipole repulsion, screening disorder and amplifying or blocking flux, achieving switching contrast $>$100 and gain $\sim$10 (Andreakou et al., 2013).
• Electrical confining/routing: Electrostatic gates or patterned slides (bilayer WSe$_2$ routers, MoSe$_2$–WSe$_2$ diodes) steer IXs between source and drain by shaping energy minima/maxima, with programmable barriers, traps, and anti-channels, and dynamic selection of output ports (Liu et al., 2019, Shanks et al., 2022).
• Indirect/bistable spinor logic gates: Spin-multistable polariton populations in cascaded nodes implement cascadable AND/NOT with ultrafast (25–50 ps) clock rates (Espinosa-Ortega et al., 2013).

A consistent unifying model is the drift-diffusion equation:

$\partial_t n = D\nabla^2 n + \mu n E - n/\tau$

where $n$ is the exciton density, $D$ the diffusion coefficient, $\mu$ the mobility, $E$ the electric field, and $\tau$ the (radiative) lifetime. Control over $D, \mu, \tau$ via vertical field, doping, and photonic environment sets the permissible circuit dynamics (Tagarelli et al., 2023, Shanks et al., 2022).

4. Performance Metrics and Bandwidth

Key experimental figures-of-merit for excitonic circuit devices are:

• Switching speed: Trion switches exhibit sub-100 fs transfer times ($\tau_\mathrm{tr}\approx65$ fs), giving tens-of-THz bandwidth; excitonic polariton gates operate at 25–50 ps per node ($\sim$20–40 GHz); indirect exciton routers limited by $\tau\sim$1–5 ns ($\sim$1 GHz) (Das et al., 2020, Espinosa-Ortega et al., 2013, Liu et al., 2019, Shanks et al., 2022).
• ON/OFF ratio/contrast: Up to an order of magnitude in vertical trion switches, $>100$ in CQW ramps, and $\sim8$ for MoSe$_2$–WSe$_2$ optical excitonic transistors (Das et al., 2020, Andreakou et al., 2013, Shanks et al., 2022).
• Energy per operation: CMOS-compatible trion switches use $<$pJ; all-optical GaAs CQW gates $10^{-13}$–$10^{-12}$ J; polariton logic nodes dominated by modest cw pump intensity (Das et al., 2020, Andreakou et al., 2013, Espinosa-Ortega et al., 2013).
• Propagation length and loss: IX systems with large $D,\tau$ enable $L_D\sim4$–$10\,\mu$m; radiative efficiency $\eta\approx1$ for field-tunable WSe$_2$ hybrid excitons allows low-loss cascaded layouts (Liu et al., 2019, Tagarelli et al., 2023).
• Fan-in/fan-out and circuit scaling: Excitonic wires support $\sim$10 devices per μm$^2$ (CQW), with cascadability to %%%%48$_2$49%%%% logic stages in spinor-polariton circuits, and valley or phase encoding extends logic state space (Andreakou et al., 2013, Espinosa-Ortega et al., 2013, Das et al., 2020).

Performance is ultimately bounded by material and device limitations, including disorder, temperature dependence, exciton lifetime, and fabrication tolerances.

5. Excitonic Analogues of Photonic Elements and Circuit Integration

Excitonic circuits mimic established photonic (and electronic) device concepts with new physical elements:

• Excitonic beam splitters and interferometers: Position-dependent inter-channel coupling $g(x)$ in parallel conduits enables 50:50 packet splitting and Mach–Zehnder interferometers. Controlled phase shifts, engineered by Stark or Zeeman effect or detuning, allow full constructive and destructive output control (Shlosberg et al., 2019).
• Excitonic filters and superlattice mirrors: Engineered regions of periodic or aperiodic site energies or coupling ($\Delta_j$, $\chi_{ij}$) act as coherent stop–pass filters or Y-junctions for packet sorting or division (Zang et al., 2016).
• Hybrid photonic–exciton–polariton circuits: Silicon nitride–TMDC–PICs with microring resonators enable valley-selective routing, GHz-class switching, and high-fidelity logic using the chiral response of interlayer excitons (Mandal et al., 2022).
• Spin- and valley-based encoding: Multiple logic values or qubits can be encoded in valley or spinor states, retrievable via selective optical polarization (Das et al., 2020, Espinosa-Ortega et al., 2013).

Integration strategies range from on-chip electrical/optical gates (2D-TMDC stacks, graphene electrodes) to fully optical microcavity lattices and programmable basin landscapes defined by patterned dielectrics or quantum wells.

6. Scaling, Challenges, and Prospective Directions

Scalability is supported by compact device footprints (sub-10 μm features), intrinsic CMOS-voltage compatibility, and near-unity radiative efficiency in TMDC and CQW materials. Challenges include:

• Temperature constraints: Certain architectures require cryogenic operation; raising operating $T$ demands larger exciton binding or robust trapping (Andreakou et al., 2013, Shanks et al., 2022).
• Material and fabrication quality: Low disorder, precise layer assembly, and nanofabrication tolerances ($<$100 nm in electrode shaping, $<$10 nm in microcavity channels) are critical (Andreakou et al., 2013, Espinosa-Ortega et al., 2013).
• Coherence and loss: Exciton dephasing times ($T_2$) and lifetimes ($\tau$) must exceed interconnect times-of-flight, while disorder and phonon coupling can limit effective coherence lengths (Zang et al., 2016, Shlosberg et al., 2019).
• Integration with conventional electronics and photonics: Cascade architectures, direct optical readout, and logic reconfigurability are achievable, but circuit-level cross-talk and routing fidelity at scale remain subjects of ongoing research (Das et al., 2020, Mandal et al., 2022).
• Dynamic tunability and programmability: Real-time shaping of potentials, or use of field-effect or optical gating for logic state control, are being advanced for reconfigurable and adaptive circuits (Liu et al., 2019, Tagarelli et al., 2023).

By leveraging the full spectrum of excitonic species, field and optical control, and hybrid architectures, excitonic circuits provide a foundational platform for ultrafast, compact, and energy-efficient optoelectronic processing, quantum information transfer, and on-chip integration with photonic networks (Das et al., 2020, Espinosa-Ortega et al., 2013, Mandal et al., 2022, Zang et al., 2016).