High-Performance Traveling-Wave MW Electrodes

• High-performance traveling-wave MW electrodes are advanced transmission lines optimized for precise impedance and velocity matching across ultra-broad bandwidths.
• Capacitively loaded TFLN and VG microstrip platforms achieve low insertion loss and near-50 Ω matching, driving efficient performance in modulators and quantum amplifiers.
• Detailed equivalent circuit models and design trade-offs provide scalable guidelines for integrating ultrafast communication components and quantum-limited devices.

High-performance traveling-wave microwave (MW) electrodes are engineered transmission lines designed to maintain impedance and velocity matching between electrical and optical (or other electromagnetic) signals across ultra-broad bandwidths, while minimizing insertion loss, dispersion, and drive voltage. Two prominent architectures—capacitively loaded traveling-wave electrodes (CL-TWEs) on thin-film lithium niobate (TFLN) and vacuum-gap (VG) microstrip lines—provide exemplary solutions for applications in ultrahigh-speed modulators and quantum-limited parametric amplifiers, respectively. The following sections delineate design principles, device structure, equivalent circuit models, performance metrics, comparative materials considerations, and best practices based strictly on benchmark experimental and theoretical results (Liu et al., 2021, Schlager et al., 10 Mar 2025).

1. Electrode Structures and Material Implementations

Capacitively Loaded Electrodes on TFLN

The CL-TWE platform integrates a thin-film X-cut LiNbO₃ (600 nm) ridge waveguide (1 μm wide, 300 nm deep) atop a 500-μm-thick quartz substrate, bonded via a 2-μm SiO₂ buffer. Electrodes consist of a central Au signal conductor (W = 50 μm, thickness ≈1.4 μm), with ground planes separated by G_unloaded = 15 μm and flanked periodically by T-rails (Λ = 50 μm, G_load = 3 μm, duty cycle = 90%). A 100-nm SiO₂ layer deposited by PECVD shields the waveguide at tight electrode gaps, suppressing SPP-induced optical loss to <0.1 dB/cm for 3-μm gaps, compared to >>10 dB/cm without this buffer (Liu et al., 2021).

Vacuum-Gap (VG) Microstrip Technology

The VG approach suspends a ground plane (Al/Nb stack, ≈300 nm Nb) above an Al or granular Al (grAl) center conductor, separated by a uniform vacuum gap h ≈ 80 nm achieved using a sacrificial ma-N 2401 resist and CPD release. Center conductors use Al (Δₛ₀ ≈ 210 μeV, α ≈ 0.6) or grAl (Δₛ₀ ≈ 351 μeV, α ≈ 0.999), widths 2–8 μm, thickness 20–50 nm. VG air-bridges every 30–50 μm provide ground continuity and mode suppression. This eliminates lossy dielectrics altogether, reducing microwave loss tangents and engineering high-capacitance, 50 Ω-matched microstrips compatible with superconducting circuits (Schlager et al., 10 Mar 2025).

Implementation	Substrate	Gap/Spacer	Buffer Layer	Width (μm)	Typical Loss (dB/cm)
CL-TWE on TFLN	Quartz	3 μm / 15 μm (electrodes)	100 nm SiO₂	50	<0.1 (optical), α ≈ 0.4
VG microstrip	High-ρ Si	80 nm (vacuum)	None	2–8	tan δ ≈ 3×10⁻⁴ (microwave)

2. Equivalent Circuit Models and Transmission-Line Analysis

Both CL-TWE and VG electrodes are analyzed as distributed transmission lines with per-unit-length parameters. For CL-TWE, the central conductor and ground define base inductance (L_unloaded) and capacitance (C_unloaded), while periodic T-rails contribute additional lumped capacitance (C_rails):

• $$C_\text{total} \simeq C_\text{unloaded} + C_\text{rails}$$,
• $L_\text{total} \simeq L_\text{unloaded}$.

The characteristic impedance and phase velocity are given by

$$Z_0 = \sqrt{\frac{L_\text{total}}{C_\text{total}}}, \qquad v_p = \frac{1}{\sqrt{L_\text{total}C_\text{total}}} = \frac{c}{n_m}$$

where $n_m$ is the microwave index. Design degrees of freedom (W, G_unloaded, G_load, T-rail duty cycle) allow fine control of $Z_0$ and $n_m$.

For VG microstrips (w ≫ h regime):

• $C' \simeq \epsilon_0 w / h$
• $L' = \mu_0 h / w + L_\text{kin}'$
• $Z_0 = \sqrt{L' / C'}$

where $L_\text{kin}'$ accounts for kinetic inductance in thin superconducting films, enabling direct tuning of $Z_0$ from ∼5–100 Ω solely by w/h.

3. Performance Metrics: Bandwidth, Loss, and Impedance Matching

CL-TWE on TFLN

Measured devices demonstrate Vπ = 3.4 V with 1.7 V·cm $V_πL$ at L_mod = 5 mm, enabled by the hybrid waveguide and narrow (3 μm) gap (Liu et al., 2021). S-parameter characterization yields $|S_{21}|$ roll-off <2 dB to 67 GHz, $|S_{11}|$ < –18 dB (DC–67 GHz), and extracted $$n_m \simeq 2.20—perfectly matched to the TFLN optical group index$$n_{g,\text{opt}} \approx 2.25$$. The main attenuation sources are conductor and dielectric losses:$$\alpha \approx \frac{R_s I_\text{unloaded} + N R_t I_\text{rails}}{2 Z_0}$$For α ≈ 0.4 dB/cm and L_mod = 5 mm, the predicted 3 dB bandwidth exceeds 110 GHz, with measured roll-off only 1.3 dB to 67 GHz.</p> <h3 class='paper-heading' id='vg-microstrip-lines'>VG Microstrip Lines</h3> <p>Cryogenic aluminum and grAl VG resonators deliver unloaded$$Q_{\text{int}} \sim 3×10^3$at single-photon occupancy, saturating up to$Q_{\text{int}} \sim 10^4$$driven by two-level-system (<a href="https://www.emergentmind.com/topics/truncated-least-squares-tls-formulation" title="" rel="nofollow" data-turbo="false" class="assistant-link" x-data x-tooltip.raw="">TLS</a>) loss saturation at higher internal photon numbers. TLS-limited loss follows:$$1/Q_{\text{int}}(P) = 1/Q_\text{res} + \frac{F \tanδ_0}{[1+(P/P_c)^\beta]^{1/2}}$ Bandwidths of several GHz are achievable, with loss tangent tan δ ≈ 3×10⁻⁴ (80-nm VG), competitive with or surpassing state-of-the-art dielectric microstrip processes (<a href="/papers/2503.07431" title="" rel="nofollow" data-turbo="false" class="assistant-link" x-data x-tooltip.raw="">Schlager et al., 10 Mar 2025</a>).</p> <p>Impedance matching in TWPAs is achieved by embedding the (large) kinetic or nonlinear inductance (L_nl&#39;) of the amplification element in <a href="https://www.emergentmind.com/topics/additive-parallel-correction" title="" rel="nofollow" data-turbo="false" class="assistant-link" x-data x-tooltip.raw="">parallel</a> with the high C&#39; of the VG microstrip, with $Z_\text{cell} = \sqrt{L_\text{nl}/C_\text{vg}} \simeq 50~\Omega$.</p> <h2 class='paper-heading' id='materials-substrate-and-fabrication-considerations'>4. Materials, Substrate, and Fabrication Considerations</h2> <p>Optical loss in CL-TWE is minimized by suppressing <a href="https://www.emergentmind.com/topics/shortest-path-percolation-spp-model" title="" rel="nofollow" data-turbo="false" class="assistant-link" x-data x-tooltip.raw="">SPP</a> excitation with the 100-nm SiO₂ buffer, allowing 3-μm electrode spacing without severe absorption penalty. Quartz substrates (ε_r ≈ 3.8) are favored over silicon (ε_r ≈ 11.7), as they:</p> <ul> <li>Counteract the increased n_m (&quot;slow-wave effect&quot;) from added capacitance,</li> <li>Reduce dielectric loss,</li> <li>Enable microwave phase velocity ($v_{p,\mu w}$) matching to the optical group velocity ($v_{g,\mathrm{opt}}$$) (<a href="/papers/2103.03684" title="" rel="nofollow" data-turbo="false" class="assistant-link" x-data x-tooltip.raw="">Liu et al., 2021</a>).</li> </ul> <p>VG structures obviate the need for dielectric spacers entirely, circumventing loss tangents contributed by SiO₂, Al₂O₃, or a-Si:H (compare: tan δ_SiO₂ ≈ 5×10⁻⁴, tan δ_VG ≈ 3×10⁻⁴), and are inherently free from dielectric dispersion. Fabrication leverages only lift-off, RIE etching, resist removal, and CPD, with no elevated thermal budgets, making the approach compatible with a range of superconducting and qubit-focused materials (<a href="/papers/2503.07431" title="" rel="nofollow" data-turbo="false" class="assistant-link" x-data x-tooltip.raw="">Schlager et al., 10 Mar 2025</a>).</p> <div class='overflow-x-auto max-w-full my-4'><table class='table border-collapse w-full' style='table-layout: fixed'><thead><tr> <th>Technology</th> <th>Loss tangent (tan δ)</th> <th>Thickest dielectric</th> <th>Special substrate?</th> </tr> </thead><tbody><tr> <td>SiO₂</td> <td>5×10⁻⁴</td> <td>50 nm</td> <td>No (standard)</td> </tr> <tr> <td>Al₂O₃</td> <td>6.5×10⁻³</td> <td>30 nm</td> <td>No</td> </tr> <tr> <td>a-Si:H</td> <td>3.6×10⁻⁵</td> <td>200 nm</td> <td>No</td> </tr> <tr> <td>VG</td> <td>3×10⁻⁴</td> <td>None (80-nm vacuum)</td> <td>No (on Si, no dielectrics)</td> </tr> </tbody></table></div><h2 class='paper-heading' id='design-optimization-and-trade-offs'>5. Design Optimization and Trade-offs</h2> <p>Key design trade-offs for high-performance traveling-wave MW electrodes include:</p> <ul> <li><strong>Electrode gap</strong>: Narrow (3 μm) gaps reduce$$V_π$$but exacerbate SPP-induced loss if not buffered; mitigation with 100 nm SiO₂ buffer enables$$V_πL$ as low as 1.7 V·cm with negligible increased loss.</li> <li><strong>Capacitive loading (T-rail period/duty cycle)</strong>: Enhances velocity matching and conductor loss reduction, but excess loading raises α at ultrahigh frequencies or reduces cutoff; periodicity Λ = 50 μm with 90% duty cycle pushes cutoff above 800 GHz in CL-TWE.</li> <li><strong>Signal width</strong>: For CL-TWE, W = 50 μm is preferred (FEM-optimized) for balanced Z₀ and conductor loss; excess width raises R_t of T-rails unnecessarily.</li> <li><strong>VG microstrip w/h ratio</strong>: Controls C&#39; and thus impedance. h = 80 nm is proven suspendable; w/h ≈ 5–20 produces Z₀ ≈ 50 Ω with appropriate L_kin for embedding in TWPAs.</li> <li><strong>Material/temperature choice</strong>: grAl preferred for large L_kin; Al for lower L_kin. Operation below 200 mK (for VG) suppresses quasiparticle losses, and highest Q_int is achieved at moderate excitation where TLS saturates.</li> </ul> <h2 class='paper-heading' id='practical-guidelines-and-application-domains'>6. Practical Guidelines and Application Domains</h2> <p>Implementation guidelines for both CL-TWE and VG technologies emphasize:</p> <ul> <li>Use thin (∼100 nm) dielectric buffers when optical loss at metal interfaces is a concern.</li> <li>Periodically loaded electrodes (CL-TWE) require T-rail pitch ≪ λ<em>μw (e.g., Λ &lt; λ</em>μw/10).</li> <li>Electroplate signal and ground conductors to &gt;1 μm to minimize conductor loss on TFLN.</li> <li>For VG electrodes, clean release (extended solvent soaks, CPD) and inclusion of ground air-bridges (every 30–50 μm) are essential for ground integrity and minimal slot mode excitation.</li> <li>Match microwave and optical velocities to maximize modulator and amplifier bandwidths ($n_m ≃ n_{g,\mathrm{opt}}$$for TFLN).</li> <li>Avoid overloading capacitance, which may trade bandwidth for further loss or dispersion above design frequencies.</li> </ul> <p>By incorporating these design and process principles, state-of-the-art CL-TWE/TFLN modulators have demonstrated sub-2 V·cm$$V_πL$, roll-off &lt;2 dB to tens of GHz, and predicted 3 dB bandwidths exceeding 100 GHz (<a href="/papers/2103.03684" title="" rel="nofollow" data-turbo="false" class="assistant-link" x-data x-tooltip.raw="">Liu et al., 2021</a>). VG microstrips, engineered as described, readily deliver ${Q_\text{int}} \sim 10^4$ under typical pump powers, loss tangents as low as 3×10⁻⁴, and impedance matching in the presence of substantial nonlinear inductances, directly supporting broadband, quantum-limited traveling-wave amplifiers (Schlager et al., 10 Mar 2025).