MIFIS FeFETs: Architecture & Scaling

Updated 9 February 2026

MIFIS FeFETs are non-volatile memory devices featuring a metal-insulator-ferroelectric-insulator-semiconductor stack that leverages ferroelectric polarization and charge trapping to enable tunable memory windows.
The architecture uses precisely controlled interlayer thickness and interface trap engineering to balance retention, endurance, and scalable integration on CMOS platforms.
Advanced stack designs and material co-engineering in MIFIS FeFETs enhance performance for multi-bit operation and neuromorphic applications while addressing critical reliability trade-offs.

A MIFIS FeFET (Metal-Insulator-Ferroelectric-Insulator-Semiconductor Ferroelectric Field-Effect Transistor) is a class of non-volatile memory device in which a ferroelectric material is sandwiched between two dielectric interlayers, traditionally with one at the gate side (metal-ferroelectric interface) and one at the channel side (ferroelectric-semiconductor interface). The combination of ferroelectric polarization and charge trapping in engineered gate stacks enables a tunable memory window, enhanced endurance, and scalable integration on CMOS platforms. Realizing these competing goals requires systematic control of interlayer thickness, interface trap densities, polarization states, and device-level operating conditions.

1. Gate Stack Architecture and Material Systems

In a prototypical MIFIS FeFET, the stack comprises, from gate to channel:

Top metal electrode (TiN, typically 10–20 nm via PVD): establishes a high work function for gate control.
Top dielectric interlayer (SiO₂ or Al₂O₃, 0.85–13 nm deposited by ALD): modulates the electric field, acts as a charge-trapping layer, and partitions bias between the gate and ferroelectric.
Ferroelectric Hf₀.₅Zr₀.₅O₂ (HZO, 9.5–13.8 nm, ALD): orthorhombic phase with remanent polarization $P_r$ ≈ 20 μC/cm², providing the bistable polarization state for non-volatility.
Bottom interfacial dielectric (SiOₓ, ~0.7–0.8 nm, O₃ oxidation): ensures CMOS compatibility, blocks direct reaction between HZO and silicon, and reduces interface state density.
P-type Si substrate (doping ∼10¹⁵–10¹⁷ cm⁻³): forms the channel for field-effect conduction.

The MIFIS topology distinguishes itself from MFIS by the insertion of a top interlayer, which disrupts direct polarization screening by the channel and introduces new trapping modes at the upper interface, enabling much larger memory windows (Hu et al., 2024, Hu et al., 2024, Hu et al., 2024, Kuk et al., 2024).

2. Memory Window Engineering: Mechanisms and Scaling

The memory window (MW), defined as the threshold voltage difference between program and erase states,

$\text{MW} = |V_{\mathrm{th,ERS}} - V_{\mathrm{th,PGM}}|,$

is governed fundamentally by two intertwined mechanisms:

A. Capacitive Division and Ferroelectric Polarization:

In the series stack, the ferroelectric ( $C_{\rm FE}$ ) and top interlayer ( $C_{\rm ox}$ ) capacitances set the voltage fraction applied across the HZO layer. The MW increases with thicker and lower-κ interlayers:

$\text{MW} \approx 2P_r \left(\frac{C_{\rm FE}}{C_{\rm ox} + C_{\rm FE}}\right), \quad C_{\rm FE} = \frac{\varepsilon_0\varepsilon_{\rm FE}}{t_{\rm FE}},\; C_{\rm ox} = \frac{\varepsilon_0\varepsilon_{\rm ox}}{t_{\rm IL}}$

where $t_{\rm IL}$ is the interlayer thickness (Hu et al., 2024, Hu et al., 2024).

B. Interfacial Charge Trapping and Multi-Stage Behavior:

MIFIS FeFETs exhibit a marked two-stage linear dependence of MW on $t_{\rm IL}$ : a lower slope for thin IL, and a higher slope beyond a threshold ( $\sim$ 1.7–2.5 nm; transition depends on material system) (Hu et al., 2024, Hu et al., 2024). This is attributed to discrete trap levels at the IL/HZO interface. As $t_{\rm IL}$ increases, both acceptor-like and donor-like traps become active, each contributing

$\Delta V_{\rm th} = Q_{\text{trap},i} \frac{t_{\rm IL}}{\varepsilon_0 \varepsilon_{\rm ox}},$

yielding steeper MW increase in the thick-IL regime before saturation occurs due to limits in field partitioning and trap occupancy.

Empirical Scaling Table: MW vs. Top SiO₂ Thickness

(from (Hu et al., 2024)) | $t_{\rm SiO_2}$ (nm) | MW (V) | |----------------------|--------| | 0 | 1.7 | | 0.85 | 3.1 | | 1.7 | 4.2 | | 2.55 | 5.4 | | 3.4 | 6.3 |

Saturation and Limiting Mechanisms:

For Al₂O₃ interlayers, MW rises up to 8.4 V in the 5–13 nm thickness range, but additional increases plateau due to diminished field across the HZO (reduced $E_{\rm FE}$ ) and incomplete retention of injected charge after programming (Hu et al., 2024).

3. Charge Trapping, Retention, and Detrapping Dynamics

MIFIS FeFETs display complex charge dynamics at both interfaces, which govern long-term data retention.

Charge Trapping Origin: During programming (positive gate bias), gate-injected holes (or electrons, depending on polarity) are trapped at the IL/HZO interface. These trapped charges, $Q_{\text{trap}}$ , boost MW but are also a major source of retention degradation (Han et al., 17 Oct 2025, Kuk et al., 2024).
Decoupling Polarization and Trapped Charge: The net threshold shift is a combined function of polarization and trapped charge:

$\Delta V_{\rm th} = \frac{P_{\rm FE} + Q_{\text{trap-G}} + Q_{\text{trap-C}}}{C_{\rm eq}},$

where $Q_{\text{trap-G}}$ and $Q_{\text{trap-C}}$ are, respectively, gate-side and channel-side trapped charges (Han et al., 17 Oct 2025). Quantitatively, $Q_{\text{trap-G}}/P_{\rm FE} \approx 170\%$ , $Q_{\text{trap-C}}/P_{\rm FE} \approx 130\%$ are observed, nearly independent of $t_{\rm IL}$ .

Detrapping Mechanisms and Retention Loss: Retention decay is overwhelmingly due to detrapping of gate-injected charge rather than FE depolarization. The dominant detrapping path switches from gate-side (WKB-limited) to channel-side (barrier-limited) as $t_{\rm IL}$ $t_{IL}$ increases:
- Thin IL: Detrapping to metal gate dominates.
- Thick IL: Lowered channel-side barrier favors de-trapping into the silicon channel, accelerating retention loss (Han et al., 17 Oct 2025).

Detrapping-induced MW loss is accurately modeled with a simple exponential:

$Q_{\text{trap-G}}(t) = Q_{\text{trap-G}}(0) e^{-k_{\rm em} t},$

with $k_{\rm em}$ the emission rate. MW reduction can reach ∼50% over 10-year extrapolated retention in thick-IL MIFIS FeFETs (Han et al., 17 Oct 2025, Hu et al., 2024).

4. Endurance, Reliability Trade-Offs, and Performance Optimization

The optimization of MIFIS stacks for multi-bit operation, high reliability, and long endurance necessitates balancing competing effects:

Memory Window vs. Endurance: Larger initial MW (i.e., thicker IL) induces higher internal fields and charge-trapping rates, reducing endurance. In SiO₂-based MIFIS:
- 3.4 nm SiO₂ (MW_initial ≈ 6.3 V): Endurance ~10⁴ cycles.
- <3 nm SiO₂ (MW_initial ≈ 3–4 V): Endurance >10⁶ cycles (Hu et al., 2024, Hu et al., 2024).
Retention Characteristics: Both erase and program retention are limited by the stability of trapped charges. For thick IL ( $>5$ nm), retention ratio after $10^5$ s can fall to ∼50%; for thin IL, retention >90% is achievable (Hu et al., 2024). Retention degradation is specifically severe after erase due to poor compensation of polarization by weakly bound trapped electrons (Kuk et al., 2024).
Optimal Interlayer Thickness: Most reports identify 2–3.5 nm as the optimal range for the IL thickness, which provides MW ≈ 4–8 V, $>75\%$ retention after extended storage times, and $>10^4$ endurance cycles (Hu et al., 2024, Hu et al., 2024, Hu et al., 2024).
Device Uniformity and Scaling: MIFIS FeFETs integrated at 7 nm node in crossbar arrays achieve compact bit-cells, large on/off ratios ( $\gtrsim10^3$ ), and superior robustness to device and interconnect non-idealities compared to alternative synaptic memories (Wang et al., 2023).

5. Advanced Stack Designs: Multi-Interlayer and Material Engineering

Complex Stack Variants:

Multi-interlayer stacks (e.g., MIFIFIS or MIFHIHFIS, Editor's term) employ additional blocking (GBL), tunnel dielectric (TDL), or charge-trapping layers to enable even larger MWs for 3D Fe-NAND and low-error multilevel operation (Hu et al., 4 Dec 2025). For example, a TiN/Al₂O₃(3 nm)/HZO(8 nm)/Al₂O₃(2 nm)/HZO(8 nm)/SiO₂(0.7 nm)/Si (the so-called "8283 stack") achieves MW >9 V but at the cost of unmitigated retention loss (25% over 10⁴ s) due to internal field-driven barrier lowering at the bottom FE/Si interface.

Mitigation Strategies:

Gate-stack redesign (e.g., insertion of HfO₂ charge-trapping layers flanking TDL), pulse amplitude minimization, and thickness scaling of interlayers substantially reduce retention loss (to <0.2% over 10⁴ s) and maintain large MWs (Hu et al., 4 Dec 2025).
Designing the top interlayer for minimal capacitive loss but high energy barrier for injected charge detrapping is critical for 10-year retention in 3D architectures (Han et al., 17 Oct 2025).

Material Co-Engineering:

Heterogeneous co-doping of the ferroelectric layer (e.g., spatial Zr/Al sublayering in HfO₂) can tune orthorhombic/monoclinic phase balance, boost remanent polarization, and simultaneously yield $>10⁴$ switching cycles with low leakage. This breaks the classical endurance-polarization trade-off that limits monodoped films (Yang et al., 22 Aug 2025).

6. Models, Governing Equations, and Design Guidelines

Design and optimization are underpinned by models that include:

1D capacitive division across series dielectrics
Coupled equations for polarization, trapped charge, and voltage drops:

$\Delta V_{\rm th} = \frac{P_{\rm FE} - (Q_{\rm it} - Q'_{\rm it})}{C_{\rm ox}}$

$E_{\rm FE} = \frac{V_{\rm G} - V_{\rm fb}}{t_{\rm FE} + (\varepsilon_{\rm FE}/\varepsilon_{\rm IL}) t_{\rm IL}}$

Rate equations for trapped charge detrapping and MW decay with time
Phase field and Preisach models for ferroelectric switching hysteresis

Design guidelines derived from empirical results (Hu et al., 2024, Hu et al., 2024, Hu et al., 2024):

For MIFIS FeFETs targeting multi-bit storage: $t_{\rm IL}$ ≈ 3–3.5 nm (SiO₂ or Al₂O₃) yields MW ≈ 6–8 V, with 10⁴ endurance cycles and 10-year retention.
For high-endurance embedded memory: $t_{\rm IL}$ ≈ 1.5–2.0 nm, MW ≈ 3–4 V guarantees >10⁶ cycles with long retention.
Co-optimization of pulse amplitude, IL thickness, and interface engineering is required to balance MW, retention, and endurance.

7. Outlook, Challenges, and Future Directions

MIFIS FeFETs have demonstrated scalable, CMOS-compatible, high-MW, and robust synaptic device operation in crossbar IMC, with large sense margins and resilience to device variation (Wang et al., 2023). However, fundamental limitations associated with retention loss (especially in erase states) and endurance, particularly in thick-IL stacks, persist. Advanced interface design, band offset engineering, dopant profile management, and dynamic biasing algorithms have been identified as necessary to bridge the gap between device- and system-level requirements for both storage-class memory and DNN accelerators (Han et al., 17 Oct 2025, Hu et al., 4 Dec 2025).

The field continues to move toward complex, highly engineered stacks—including multilayer charge-trapping and asymmetric dielectric structures—while integrating sophisticated physical models into the design automation flow. This approach enables fine control over non-idealities while maintaining compatibility with state-of-the-art logic nodes and neuromorphic computing applications.

Key References:

(Hu et al., 2024, Hu et al., 2024, Hu et al., 2024, Han et al., 17 Oct 2025, Kuk et al., 2024, Wang et al., 2023, Hu et al., 4 Dec 2025, Yang et al., 22 Aug 2025)