Modulo Analog-to-Digital Converters (ADCs)

• Modulo ADCs are systems that apply a nonlinear modulo operator to wrap high dynamic-range signals into a limited range before quantization.
• They employ specialized digital unfolding algorithms, like B²R² and OMP, to recover the original signal with low mean-squared error.
• Hardware implementations and reconstruction strategies yield up to 40 dB improvement compared to conventional ADCs under optimal oversampling conditions.

A Modulo Analog-to-Digital Converter (ADC) is an acquisition system in which a nonlinear folding (modulo) operator is placed before quantization and sampling, allowing signals of arbitrarily large dynamic range to be mapped into the finite input range of a conventional ADC. The ADC thus only digitizes the "wrapped" signal, while specialized digital algorithms subsequently recover or "unfold" the original signal from the folded, quantized samples. This architecture enables robust, low-cost, and low-energy digitization of high-dynamic-range (HDR) signals, with performance metrics that surpass or match those of conventional ADCs under appropriate conditions. A unified theoretical and algorithmic foundation for modulo ADCs appears in recent research spanning analog design, digital signal processing, and information theory.

1. Mathematical Model and Nonlinear Front-End

Let $f(t)$ be the real-valued analog input, and $\lambda > 0$ the threshold defining the ADC's native dynamic range (DR). The folding (modulo) operator is defined as: $$\mathcal{M}_\lambda(f(t)) = (f(t) + \lambda) \bmod 2\lambda - \lambda,$$ so that $|\mathcal{M}_\lambda(f(t))| \leq \lambda$ for all $t$ (Azar et al., 2022, Bernardo et al., 2 Jan 2025, Zhu et al., 2024). After uniform sampling at times $t = nT_s$ and quantization, the digital output is: $y[n] = \mathcal{M}_\lambda(f(nT_s)),$ possibly with quantization and folding side-information (see Section 3).

This front-end prevents amplitude-based overflow/clipping, as $f(t)$ of arbitrary magnitude is mapped into the principal interval $[-\lambda,\lambda]$. The core task shifts from ADC hardware-level DR to digital recovery of the unfolded sequence.

2. Sampling Theory and Identifiability

A key result is that bandlimited signals can be uniquely identified from their modulo samples as long as the sampling rate exceeds (but need only marginally exceed) the Nyquist rate: $\omega_s > 2\omega_m,$ where $\omega_m$ is the one-sided input bandwidth and $\omega_s = 2\pi/T_s$ (Azar et al., 2022, Mulleti et al., 2023, Bernardo et al., 2 Jan 2025). Below Nyquist, identifiability fails due to ambiguity in resolving the integer fold sequence.

For specific signal classes, including finite rate-of-innovation (FRI) and shift-invariant (SI) spaces, conditions are further refined: perfect or minimal-sample reconstruction is possible with sample rate just above the critical density, as long as the modulo front-end preserves all temporal "innovation" events and appropriate algorithms are used (Mulleti et al., 2022, Kvich et al., 2024).

3. Reconstruction Algorithms and Error Performance

General Reconstruction: B²R² Algorithm

The "Beyond-Bandwidth Residual Reconstruction" (B²R²) framework formalizes recovery as follows (Azar et al., 2022, Azar et al., 2021):

• Represent each modulo sample as

$$y[n] = f(nT_s) + z[n],\quad z[n] \in 2\lambda\mathbb{Z},\quad z[n] = 0\ \text{if} \ |f(nT_s)| < \lambda.$$

• Express residual $z[n]$ as a sparse, finite-support sequence (nonzero only at indices corresponding to threshold crossings).
• In Fourier space, exploit the fact that the DTFT of the residual polynomial occupies out-of-band frequencies, while the bandlimited $f[n]$ has energy confined to in-band.
• Solve a constrained least-squares problem for $z[n]$ by matching the high-frequency spectral content, leveraging projected gradient descent, support reduction ("peeling"), and residual quantization.
• Reconstruct $f[n] = y[n] - z[n]$, and interpolate to obtain $f(t)$.

This approach achieves low mean-squared error (MSE) at moderate oversampling (OF ≈ 4–6), improving by 10–40 dB over previous high-order-difference or Chebyshev methods for a given rate, DR, and SNR (Azar et al., 2022, Azar et al., 2021, Shah et al., 2024).

1-Bit Folding Side-Information and OMP

In architectures providing a 1-bit folding indicator per sample, exact unfolding is possible via simple accumulation when the oversampling factor $\mathrm{OF} > 3$ and quantizer resolution $b > 3$:

• Estimate fold increments from the side channel.
• Integrate to recover the integer fold count $k[n]$.
• Unwrap: $f[n] = y[n] + \Delta k[n]$ (Bernardo et al., 2 Jan 2025, Bernardo, 2024).

In the absence of explicit side information, unfolding becomes a sparse recovery problem for the fold-difference sequence (using, e.g., orthogonal matching pursuit, OMP), with similar sufficient conditions but slightly higher bit-depth requirements ($b > 3 + \log_2 \delta$) (Bernardo et al., 2 Jan 2025).

Sliding DFT, compressed sensing/LASSO, and dynamic programming plus OMP can further accelerate and robustify unfolding under quantization and noise (Bernardo, 2024, Shah et al., 2024, Zhu et al., 2024).

Error Scaling

Modulo ADCs admit the following MSE scaling laws when the folding/unfolding is successful: $$\text{MSE}_{\text{modulo}} = \mathcal{O}\left(\frac{1}{\mathrm{OF}^3}\right), \quad \text{MSE}_{\text{conv ADC}} = \mathcal{O}\left(\frac{1}{\mathrm{OF}}\right),$$ demonstrating the inherent noise-averaging and effective DR extension benefits of the modulo approach (Bernardo et al., 2 Jan 2025, Zhu et al., 2024, Li et al., 27 Nov 2025).

4. Hardware Architectures and Implementation

Analog Realizations

Recent advances produce efficient, integrator-based and FPGA-enabled analog front-ends for modulo folding, which operate at high bandwidth (up to 400 kHz) and allow dynamic-range expansion factors exceeding 100× (Zhu et al., 2024, Li et al., 27 Nov 2025). Key innovations include:

• Analog folding blocks based on Schmitt triggers and integrators for arbitrary high folding rates, unconstrained by counter speed.
• Multi-bit feedback (via digital-to-analog converters and fast FPGA control) to stabilize the wrap magnitude and minimize overshoot.
• Co-design with high-speed comparators and windowed feedback ensuring folding accuracy within a few millivolts.

The overall sampling chain consists of: input → modulo fold → optional mixer/LPF (for spectral conditioning) → quantizer (ADC) → digital recovery algorithm (Kvich et al., 20 Jan 2025, Bernardo et al., 2 Jan 2025).

Bit-Efficient Multichannel Schemes

Bit-efficient two-channel modulo ADC systems use only one fully quantized channel plus a compact integer-difference index, leveraging efficient Chinese Remainder Theorem (ECRT) decoding to maintain an overhead of at most 1–2 bits per sample relative to a full-range ADC, even for large DR (Yan et al., 20 Jan 2026). This substantially reduces ZIP-powered sensor network bit budgets as compared to independent quantization of both folded channels.

Hardware Performance Benchmarks

Prototype systems demonstrate:

• HDR capture at 60× native range and 5-bit ENOB enhancement at moderate quantizer resolution (Zhu et al., 2024).
• FPGA-based platforms with sub-25 ns feedback latency, loop stabilization, and real-time recovery over 400 kHz bandwidth at quantization fidelity nearly matching the oscilloscope baseline (Li et al., 27 Nov 2025).
• Analog and mixed-signal prototypes that function robustly under pre-modulo noise, gain mismatch, or component non-idealities, provided corresponding digital correction is employed (Mulleti et al., 2023, Zhu et al., 2024).

5. Applications and Impact Domains

Modulo ADCs are suited for domains where DR is a major bottleneck:

• Cognitive radio and radar: simultaneous acquisition of strong and weak bands, overcoming co-channel interference and front-end saturation (Liu et al., 2022, Bernardo et al., 2 Jan 2025).
• Massive MIMO: receiver chains with modulo folding enable high spectral efficiency even at 1–2 bit quantization, without the power expense or precision limitations of classical architectures (Liu et al., 2022).
• Sensing highly non-stationary or impulsive signals: e.g., FRI models, shift-invariant spaces, and multi-band signals are supported through appropriate unfolding kernels and algorithms (Mulleti et al., 2022, Kvich et al., 2024).
• Low-power or area-constrained nodes: folding mitigates the need for high-resolution, high-area, or high-power ADCs (Krishna et al., 2019, Ordentlich et al., 2018).
• Real-time hardware, FPGA/SoC platforms: embedded dynamic-range control, DSM integration, and compressive recovery for resource-limited or bandwidth-constrained signal processing (Li et al., 27 Nov 2025, Yan et al., 20 Jan 2026).

6. Trade-Offs, Design Considerations, and Open Challenges

Sampling Rate vs. Dynamic Range

Modulo ADCs shift the design constraint from the analog DR to a sampling rate/algorithmic complexity trade-off. Unique, accurate recovery is possible just above Nyquist for most bandlimited classes, but practical implementations must account for:

• Additional oversampling at low DR ($\lambda \ll \|f\|_\infty$); smallest folding thresholds increase the required OF to preserve robustness against quantization and noise (Shah et al., 2024, Zhu et al., 2024).
• Quantizer resolution; for systems with side-channel information, 3–4 bits suffice, but higher-DR or challenging folding patterns benefit from increased bit-depth and/or folding indicator streams (Bernardo et al., 2 Jan 2025, Shah et al., 2024).

Algorithmic Robustness and Complexity

New algorithms such as B²R², sliding-DFT recovery, LASSO-B²R², and fast ECRT exploit sparsity and predictability in the folding residual, outperforming earlier finite-difference approaches in speed, robustness, and sample efficiency (Bernardo, 2024, Shah et al., 2024, Yan et al., 20 Jan 2026).

Hardware Limitations

Analog nonidealities (slew rate, integrator drift, finite DAC/ADC bandwidth, comparator hysteresis) induce errors that must be addressed by design margin or digital correction (Zhu et al., 2024, Li et al., 27 Nov 2025, Mulleti et al., 2023). Synchronization between folding events, ADC conversions, and folding-state readout is critical for real-time recovery.

Extension to Non-Bandlimited and Multichannel Inputs

Extensions to SI spaces, multi-band, and FRI models have been demonstrated, but open challenges remain for:

• Double or higher-order folding in multidimensional (e.g., imaging) systems.
• Cyclostationary, impulsive, or nonstationary signals with rapidly time-varying statistics.
• Fully blind algorithms adaptive to input spectrum and folding patterns (Weiss et al., 2021, Weiss et al., 2021, Weiss, 2024).

7. Comparative Summary and Outlook

Modulo ADCs provide a unified framework for capturing and digitizing high-dynamic-range signals with near-minimal bit budgets, marginally increased sampling rates, and feasible hardware complexity. They generalize and strictly improve over classical clipping/companding ADCs, and strong empirical and theoretical results confirm their practicality and performance advantages in prototyped analog, digital, and mixed-signal implementations (Azar et al., 2022, Bernardo et al., 2 Jan 2025, Zhu et al., 2024, Li et al., 27 Nov 2025, Shah et al., 2024, Yan et al., 20 Jan 2026).

The field is rapidly developing, with active research in robust blind recovery, bitrate minimization, multi-channel resource allocation, and high-rate real-time platforms for telecommunications, scientific instrumentation, radar, and IoT. Modulo ADCs are poised to become a standard tool for efficient HDR digitization.