Noisy Intermediate-Scale Quantum (NISQ)

• NISQ computing is defined as quantum processors with 50–1000 qubits that operate without comprehensive error correction, where noise significantly limits circuit depth and algorithm complexity.
• It enables experimental milestones such as quantum advantage in random circuit and Gaussian boson sampling, and supports hybrid algorithms like VQE and QAOA for chemistry and optimization.
• Research in NISQ drives advancements in error mitigation, noise modeling, and scalable hardware architectures that are foundational for the transition to fault-tolerant quantum computing.

Noisy Intermediate-Scale Quantum (NISQ)

Noisy Intermediate-Scale Quantum (NISQ) computing refers to the class of quantum processors operating in the regime between few-qubit laboratory prototypes and fully error-corrected, large-scale fault-tolerant quantum computers. NISQ devices possess 50–1000 physical qubits, lack comprehensive quantum error correction (QEC), and are characterized by non-negligible noise processes that fundamentally constrain circuit depth and algorithmic complexity. The NISQ era is marked by substantial experimental milestones, including demonstrations of quantum computational advantage (e.g., random circuit sampling and Gaussian boson sampling), as well as the development of quantum-classical hybrid algorithms for chemistry, optimization, and machine learning. However, the overarching technological limitations of this regime, specifically in coherence time, gate fidelity, and noise stability, sharply limit the scope of practical quantum advantage and define NISQ as a critical—but ultimately transitional—epoch in quantum information science (AbuGhanem et al., 2023, Cheng et al., 2023, Preskill, 2018, Ezratty, 2023).

1. Regime Definition, Performance Metrics, and Noise Characteristics

A NISQ device is defined as a programmable quantum processor with $50 \lesssim N_\text{physical qubits} \lesssim 1000$, typically incorporating no full QEC. The hallmark of NISQ is the presence of significant noise sources—energy relaxation ($T_1$), dephasing ($T_2$), control and measurement imperfections, crosstalk, and leakage—that place strict upper limits on the effective circuit depth ($d$) and qubit count ($N$) that can be utilized for computation (AbuGhanem et al., 2023, Preskill, 2018, Ezratty, 2023).

Key figures of merit for a representative Sycamore-class device:

Metric	Value Range	Notation
Physical qubits	50–1000	$N$
$T_1$	20–100 μs	$T_1$
$T_2$	10–50 μs	$T_2$
Single-qubit gate fidelity	0.998–0.999	$T_1$0
Two-qubit gate fidelity	0.994–0.996	$T_1$1
Measurement fidelity	0.95–0.99	$T_1$2
Single-qubit error	$T_1$3	$T_1$4
Two-qubit error	$T_1$5	$T_1$6

The quantum volume metric $T_1$7 encapsulates the practical tradeoff between register width and coherent circuit depth. NISQ processors can reliably execute circuits with $T_1$8 before noise dominates the output (Cheng et al., 2023).

Noise in NISQ devices is stochastic and time-dependent, with drifts in $T_1$9, $T_2$0, and gate fidelities observed over calibration cycles and spatial heterogeneity across physical sites. This instability complicates reproducibility and reliability, requiring real-time monitoring and calibration (Dasgupta et al., 2021, Waring et al., 2024).

2. Hardware Architectures

The principal NISQ architectures include:

Superconducting Qubits: Fast gate times (10–50 ns), moderate $T_2$1, $T_2$2 (10–100 μs), lithographic scalability, and integration suitability. Limitations include cryogenic requirements ($T_2$310–20 mK), calibration drift, and microwave crosstalk. Exemplified by Google Sycamore ($T_2$4, $T_2$5), IBM Eagle ($T_2$6), USTC Zuchongzhi ($T_2$7) (AbuGhanem et al., 2023, Cheng et al., 2023).

Trapped Ions: Superior coherence ($T_2$8 s), very high gate fidelity ($T_2$9), and all-to-all connectivity in few-qubit chains. Limitations: slower gate speeds (10–100 μs), mode crowding, and scaling complexity (Cheng et al., 2023).

Photonic Systems: Room-temperature operation, negligible decoherence, and high-rate sampling capability. Limitations: probabilistic photon sources, photon loss, and lack of deterministic entangling gates. Architecture: Boson sampling (Jiuzhang), Gaussian Boson Sampling (Borealis) (AbuGhanem et al., 2023).

Other platforms in the NISQ regime include semiconductor spin qubits, neutral-atom arrays, NV centers, and liquid-state NMR systems, each with unique strengths and scalability bottlenecks (Cheng et al., 2023).

3. Quantum Advantage and Supremacy Experiments

NISQ devices have enabled quantum computational advantage for specific sampling tasks thought to require exponential ($d$0) classical resources, with the quantum runtime scaling polynomially.

Key demonstrations:

• Google Sycamore: 53 qubits, 20-cycle random circuit sampling, $d$1 s, classical simulation estimated at $d$2 years (later reduced to $d$315 h by improved classical algorithms), sample fidelity $d$4 (AbuGhanem et al., 2023).
• USTC Zuchongzhi: 66 qubits, similar random circuit sampling, achieving $d$54.8 $d$6 year classical time for verification (AbuGhanem et al., 2023).
• Photonic (GBS/Boson Sampling): Jiuzhang 2.0: classical time estimation $d$7–$d$8 s, quantum sampling rate improvement up to $d$9 over classical (AbuGhanem et al., 2023).

Despite these milestones, such experiments do not generalize to universal quantum advantage in scientifically or commercially relevant domains under current NISQ constraints (Ezratty, 2023).

4. NISQ Algorithms and Applications

Proof-of-principle applications compatible with shallow, noisy circuits include:

• Variational Quantum Eigensolver (VQE): Hybrid optimization to approximate molecular ground states. Demonstrated up to 6–8 qubits with chemical accuracy ($N$0 Ha) reached in small systems (AbuGhanem et al., 2023, Preskill, 2018).
• Quantum Approximate Optimization Algorithm (QAOA): For classical combinatorial optimization. Demonstrated Max-Cut on 19-node graphs, $N$1, and Rydberg atom arrays for independent set extraction up to 289 atoms (AbuGhanem et al., 2023).
• Quantum Machine Learning: Quantum-enhanced supervised/unsupervised learning, quantum kernels, quantum neural networks, and applications in finance (option pricing, credit risk). Demonstrations are limited to $N$2 (AbuGhanem et al., 2023, Yang et al., 2019, Khan et al., 2019).
• SDP Solvers: NISQ algorithms for semidefinite programming leverage quantum devices to estimate lower-dimensional ansatz overlaps, bypassing exponentially hard minimization in the full Hilbert space for many important instances (Bharti et al., 2021).

The persistent bottleneck is the inability to execute deep, complex circuits or large-scale optimizations before coherence and gate errors eliminate computational signal (Ezratty, 2023, Brandhofer et al., 2023).

5. Noise Modeling, Error Mitigation, and Compilation

Noise Modeling: NISQ noise is described using operator-sum/Kraus maps, Lindbladian dynamics, or Pauli error models. Key error channels are depolarizing, amplitude damping, and dephasing. Methods for precise characterization include bootstrapped subcircuit testing and total variation distance benchmarking (Riera-Sàbat et al., 10 Jun 2025, Dahlhauser et al., 2020).

Error Mitigation: With full QEC out of reach, several strategies are implemented:

• Zero-Noise Extrapolation (ZNE): Run circuits at artificially raised noise rates, fit, then extrapolate to $N$3 (AbuGhanem et al., 2023, Preskill, 2018).
• Probabilistic Error Cancellation (PEC): Sample inverses of noise channels using quasi-probabilities, unbiased but sampling-cost prohibitive for deep circuits (AbuGhanem et al., 2023).
• Readout error calibration: Invert the measurement error matrix (AbuGhanem et al., 2023).
• Dynamical Decoupling, Randomized Compiling: Tailor pulse sequences to suppress dephasing and stochastic noise (AbuGhanem et al., 2023, Ezratty, 2023).

Compiler and Mapping: Noise-aware compilation exploits daily calibration data to prefer high-fidelity qubits and links, minimizing added SWAPs and cumulative error. Formulations leverage SMT and heuristic algorithms to address the NP-hard mapping and routing problem (Murali et al., 2019, Paler et al., 2018, Murali et al., 2019).

Time-Dependent Noise Adaptation: Explicit pruning of qubits and gates based on up-to-date calibration can increase circuit fidelity by up to 52% for long chains, extending device operational life (Waring et al., 2024).

Circuit Approximation: Circuit re-synthesis and gate-pruning under unitary fidelity constraints yield shallower, more robust approximations, crucial for deep circuits on NISQ hardware (Wilson et al., 2021).

6. Simulation, Benchmarking, and Utility

Simulation Frameworks: Classical simulation of NISQ devices is resource-intensive due to exponential state spaces. Efficient simulators (e.g., SANQ) combine Monte Carlo error propagation with architectural modeling of control circuits, validated directly against device data (Li et al., 2019).

Quantum Simulation with NISQ Noise: Quantum simulators can leverage device noise to mimic the error profiles of target quantum networks or protocols, converting “adversarial” noise into a resource for realistic benchmarking of large-scale quantum network components (Riera-Sàbat et al., 10 Jun 2025).

Benchmarks and Metrics:

• Quantum Volume: $N$4 (Cheng et al., 2023).
• Success Probability and Error Thresholds: No algorithm tested on ArsoNISQ tolerates on average even a single error; to achieve $N$5 success in circuits with $N$6 gates, per-gate errors must be $N$7 (Brandhofer et al., 2023).
• Stability Metrics: Hellinger distance quantifies device stability over time, highlighting the necessity of dynamic calibration and error-aware benchmarking (Dasgupta et al., 2021).

7. Prospects, Limitations, and Transition to Fault-Tolerance

Utility Window: The plausible near-term window for practical NISQ advantage is vanishingly small, closely bounded by the twin requirements of $N$8 qubits, gate errors $N$9, and shallow ($N$0) circuits with advanced error mitigation (Ezratty, 2023, Brandhofer et al., 2023).

Industrial and Scientific Relevance: NISQ-enabled advantage is limited to highly structured, noise-robust problems (narrowly defined sampling, modest-scale analog simulation, specialized co-processing), but remains unattainable for most “killer applications” without significant scaling in both hardware quality and error-mitigation tooling (AbuGhanem et al., 2023, Ezratty, 2023).

Roadmap: Sustained progress necessitates

• pushing gate fidelities below $N$1 at $N$2,
• furthering error-mitigation strategies,
• developing automated, noise-adaptive compilation,
• and advancing analog and hybrid quantum-classical methods in parallel with scalable QEC research (AbuGhanem et al., 2023, Ezratty, 2023, Cheng et al., 2023).

Transition to Fault Tolerance: Large-scale, universal quantum computation will require active QEC, with projected demands of $N$3 physical qubits per logical qubit and gate error rates $N$4 for meaningful error suppression. NISQ systems, through iterative advances in hardware, noise modeling, and hybrid protocol development, provide the essential groundwork for this transition (AbuGhanem et al., 2023, Preskill, 2018, Cheng et al., 2023).

Summary Table: NISQ vs. Fault-Tolerant Regimes

Criterion	NISQ	Fault-Tolerant Quantum Computing
Qubit count	$N$5 (physical)	$N$6 (physical)
Gate fidelity	$N$7–$N$8	$N$9
Error correction	None, error mitigation only	Full quantum error correction
Circuit depth	$T_1$0 (limited by noise)	$T_1$1–$T_1$2 (protected)
Application scope	Benchmarking, demo, hybrid	Universal, scalable

NISQ is thus a crucial but limited era, providing testbeds, early algorithmic validation, and hardware integration for quantum information processing, while the ultimate roadmap mandates overcoming inherent noise via comprehensive fault tolerance and scalable architectures. The full promise of quantum simulation, optimization, and quantum-enhanced machine learning is expected to be realized in the ensuing era of fault-tolerant quantum computation (AbuGhanem et al., 2023, Cheng et al., 2023, Ezratty, 2023, Preskill, 2018).