Non-Volatile Photonic Gate Array

• Non-volatile photonic gate arrays are reconfigurable platforms that store optical configurations persistently without continuous power.
• They leverage diverse tuning mechanisms—including phase-change materials, memristive switching, ferroelectric domain control, and MEMS—to set and maintain optical states.
• Integrated with modular components like Mach–Zehnder interferometers and ring resonators, NV-FPPGAs support scalable optical processing for switching, computation, and filtering.

A non-volatile field-programmable photonic gate array (NV-FPPGA) is a reconfigurable integrated photonic platform in which the configuration of optical gates or phase-shifting elements can be programmed into memory states that persist without sustained electrical or optical power. This paradigm enables zero-static-power operation and high integration density, directly addressing scalability and sustainability challenges that afflict conventional volatile phase-shifting approaches (thermo-optic, carrier-injection, or analog EO) in photonic integrated circuits (PICs). NV-FPPGA architectures leverage a range of non-volatile tuning mechanisms—including phase-change materials (PCMs), memristive phase shifters, ferroelectric domain switching, and mechanically latched MEMS—integrated with established photonic circuit building blocks such as Mach–Zehnder interferometers (MZIs), ring resonators, and multimode interferometers (MMIs). Their non-volatile states are programmed by one-shot electrical, optical, or mechanical stimuli, and held passively over long timescales, enabling field-configurable functionalities for optical processing, switching, neuromorphic and quantum photonic computation, and post-fabrication trimming.

1. Non-Volatile Photonic Tuning Mechanisms

NV-FPPGAs realize persistent photonic state programming via several distinct material and device mechanisms:

• Phase-Change Materials (PCMs): Chalcogenide-based PCMs such as Ge$_2$Sb$_2$Te$_5$ (GST), Sb$_2$Se$_3$, and Sb$_2$S$_3$ switch between amorphous and crystalline phases with pronounced and non-volatile refractive-index contrast. These transitions are triggered via electrical Joule heating, optical pulsing, or both, with energy per event ranging from tens of picojoules (Sb$_2$Se$_3$, $\sim$10 pJ/π phase) up to nanojoules (GST, 1–100 nJ), with retention exceeding years at moderate temperatures (Delaney et al., 2021, Chen et al., 23 Jun 2025, Blundell et al., 2024, Fang et al., 2021, Chen et al., 2023, Xu et al., 2018, Perez-Lopez et al., 2020).
• Memristive/Resistive Switching: Memresonators combine a resistive-switching oxide (e.g., ALD Al$_2$O$_3$) integrated with III-V/Si microring resonators or MZI phase shifters. Phase is set by the formation and rupture of conductive filaments in the oxide under sub-5 V electrical pulses—enabling SET/RESET transitions that shift optical phase via carrier plasma-dispersion and remain stable without hold bias ($<0.36$ pJ, sub-ns, retention $>12$ h) (Tossoun et al., 2023).
• Ferroelectric Domain Switching: Hybrid ferroelectric silicon photonics utilize the non-volatile remanent polarization of, e.g., barium titanate (BTO) or Hf$_{0.5}$Zr$_{0.5}$O$_2$ gate stacks to set the local electric field and, consequently, the refractive index in an EO waveguide region. States are set by short, sub-5 V electrical pulses, with static power consumption reduced to nW–fJ per π phase shift and retention inheriting from ferroelectric memory technology ($>10^{11}$ cycles possible) (Catalá-Lahoz et al., 12 Jan 2026, Tang et al., 2022).
• Mechanically Latched MEMS: Electrostatic MEMS actuators implement mechanically latched digital tuning in MZI arms and directional coupler gaps, yielding truly passive retention (zero electrical connection once set), sub-ms mechanical switching, and insertion loss comparable to best-in-class thermally tuned units (Tao et al., 10 Jan 2026).

A comparison of key metrics across different mechanisms is summarized below.

Technology / Ref	Switching Energy	Insertion Loss	State Retention	Endurance	Notes
Sb$_2$Se$_3$ PCM (Delaney et al., 2021, Chen et al., 23 Jun 2025)	10–30 pJ/π	<0.1 dB / element	Years	$>10^3$–$10^6$	Multi-bit, ultralow-loss
GST PCM (Xu et al., 2018, Perez-Lopez et al., 2020)	100 pJ–10 nJ	~1 dB / element	Decades	$10^8$-$10^{12}$	Extensively studied, higher loss
Memresonator (Tossoun et al., 2023)	0.15 pJ SET/0.36 pJ RESET	~0.048 dB	>12 h	≥1000 cycles	Fastest switching, III–V/Si hybrid
Ferroelectric Si–BTO (Catalá-Lahoz et al., 12 Jan 2026)	~45 fJ/π	~1.5 dB/PUC	>days	n/a	No thermal crosstalk, 80 ns switches
FeFET-driven (Tang et al., 2022)	≤3.3 nJ	~0.3 dB/π (mod loss)	>years	$>10^{11}$	Multistate, CMOS-compatible
MEMS mechanical (Tao et al., 10 Jan 2026)	~μJ (per config)	0.5–0.7 dB / TBU	Infinite	n/a	Zero hold power, digital states

2. Circuit Building Blocks and Integration

The core reconfigurable elements of NV-FPPGAs are modular photonic units (phase shifters, couplers, MZIs, MMIs, ring resonators) designed for seamless integration into large-scale mesh networks:

• MZI- and MMI-Based Topologies: Rectangular (Clements, Reck), triangular, and hexagonal meshes are universal linear optical networks, realizable with programmable MZI or MMI nodes. PCM elements are integrated as variable phase shifter patches or pixelated patterning regions (single-phase or binary “digital” pixels), enabling unitary matrix synthesis and reconfigurable power splitting (Chen et al., 23 Jun 2025, Blundell et al., 2024, Delaney et al., 2021, Chen et al., 2023).
• Microring and Coupler Architectures: Tunable ring resonators—via localized PCM, memresonator, or Sb$_2$S$_3$ patches—allow for reconfigurable filtering, switching, and delay-line implementations, with non-volatile control over resonance and coupling (Fang et al., 2021, Tossoun et al., 2023, Xu et al., 2018).
• Mechanically Latched Node Arrays: MEMS-based digital gate units can be tiled in regular 2D meshes, each independently set to one of $n^4$ discrete states, covering the (κ, φ) parameter space for coupling ratio and phase with sufficient granularity for practical performance parity with continuously tunable FPPGAs (Tao et al., 10 Jan 2026).
• Hybrid and Electronic Control: Direct electrical, optical, or crossbar matrix addressing strategies (e.g., 1T1R, 2T1C topologies for PCM/FeFET arrays) are used for scalable programming, supporting parallel or pipelined configuration of hundreds to thousands of nodes (Tang et al., 2022, Chen et al., 2023).

3. Performance Benchmarks and Comparison

Key parameters defining NV-FPPGA suitability for large-scale applications include switching energy, speed, insertion loss, static power, retention, endurance, and optical crosstalk.

• Energy and Speed: Switching energy for leading PCM and memresonator-based units is orders of magnitude lower than for thermo-optic analogues (e.g., 0.15–0.36 pJ for memresonators (Tossoun et al., 2023); <30 pJ for Sb$_2$Se$_3$ PCM (Delaney et al., 2021, Chen et al., 23 Jun 2025); ~3 nJ for FeFETs (Tang et al., 2022)). Programming time ranges from 300 ps (memresonator) to 80 ns (Si–BTO ferroelectric) and up to 10 ms (FeFETs).
• Optical Loss and Fidelity: The best PCM (Sb$_2$Se$_3$) and memresonator-based architectures achieve insertion loss below 0.05–0.1 dB per programmable element (Delaney et al., 2021, Tossoun et al., 2023), enabling cascaded meshes of $>50$ gates with aggregate loss manageable by on-chip gain or low-loss routing. MEMS (0.6–1.0 dB), GST PCM (0.5–1 dB), and BTO (1.48 dB) are higher, with device or process-specific paths for reduction.
• Scalability: Device footprints of 5–30 μm per phase-shifter are commonplace for Sb$_2$Se$_3$ PCM and memresonators (Blundell et al., 2024, Tossoun et al., 2023), with mesh densities up to $\sim100$ gates/mm². Multichannel addressing and optical programming (for digital pixel-based direct-write architectures) allow for array scaling to thousands of elements with negligible aggregate static power.
• Retention and Reliability: PCMs provide retention over years at $T<100\,^\circ$C; memresonators reliably exceed 12 h drift-free operation; ferroelectric domains are fundamentally non-volatile; MEMS latches are mechanically locked indefinitely (Delaney et al., 2021, Tossoun et al., 2023, Tao et al., 10 Jan 2026). Endurance (number of switching cycles before degradation) spans $10^3$–$10^6$ for PCM elements (buoyed by careful thermal/stress management), $>10^{11}$ for FeFETs, and essentially unlimited for MEMS.
• Crosstalk and Stability: Engineered optical and thermal isolation (e.g., device spacing, isolation trenches, oxide encapsulation) enables crosstalk below –30 dB for Sb$_2$S$_3$ PCM and MEMS architectures. PCMs intrinsically remove thermal crosstalk by eliminating steady-state heating. Negative thermo-optic coefficients in Sb$_2$S$_3$ further aid environmental stability (Fang et al., 2021).

4. Programming, Control, and Configuration Workflows

Programming workflows in NV-FPPGAs are specialized for the non-volatile and often discrete or multistate nature of the underlying devices.

• Program-and-Verify Closed-Loop: Closed-loop “program-and-verify” algorithms empower repeatable, multi-level setting in the presence of device and environmental drift—particularly essential for stochastic PCM transitions. This involves iterative pulse application, optical or electrical monitoring, and fine-tuning until the desired transmission/phase state is stably achieved (precision as fine as $<0.1\%$ in Sb$_2$Se$_3$ NEO-PGA (Chen et al., 23 Jun 2025)).
• Digital Pixel Patterning and Direct Write: PCM pixel-based direct-writing (optically addressed, typically with sub-μm resolution) affords digital “bit” control over phase and amplitude at unprecedented densities. Fast multi-pulse scanning allows fully reconfiguring a photonic mesh in less than a millisecond (Blundell et al., 2024).
• Electrically Addressed Crossbars/1T1R: In electronic crossbar addressing, one-transistor-per-element or word/bit/selection line routing schemes enable scalable, parallelized programming. For FeFETs or memresonators, write/erase cycles are row/col-selectable, with suppression of sneak paths by asymmetric pulse protocols (Tang et al., 2022, Tossoun et al., 2023).
• Mechanical/Swarm Optimization: Mechanically latched MEMS arrays are programmed by sequentially stepping each TBU into its n-state configuration, then running global discrete optimization (e.g., swarm algorithms) to minimize network-wide cost functions (e.g., spectral fitting, path extinction) in the space of all combinatorial state assignments (Tao et al., 10 Jan 2026).

5. Application Domains and Demonstrated Systems

NV-FPPGAs target a variety of high-impact photonic computation and signal processing workloads:

• Reconfigurable Optical Switching Fabrics: Demonstrated 4×4–32×32 optical circuit switches, including nonblocking meshes and high-Q resonator arrays, have been realized with mean crosstalk below –25 dB and reconfigurable in seconds to ms (Chen et al., 23 Jun 2025, Xu et al., 2018, Tossoun et al., 2023).
• On-Chip Matrix–Vector Multiplication: Non-volatile MZI meshes enable programmable unitary transformations for O(N²)-sized matrix–vector multipliers, critical for optical neuromorphic acceleration and quantum photonics, while holding weights and routing without power (Tang et al., 2022, Delaney et al., 2021, Chen et al., 2023).
• Quantum Circuitry: Universal unitary mesh arrangements synthesized with non-volatile phase shifters are used to implement quantum gates, post-fabrication trimming, and dynamic reconfiguration for quantum error correction or teleportation (Fang et al., 2021, Tang et al., 2022).
• Programmable Filtering and Signal Processing: Dynamic IIR/FIR filters, broadcast splitters, and multi-ring coupled-resonator systems have been achieved, leveraging the multi-bit programmability and low insertion loss of PCM and ferroelectric-based FPPGAs (Catalá-Lahoz et al., 12 Jan 2026, Tossoun et al., 2023).
• Advanced Functionality—Direct-write MMIs, Pixelation: Ultrahigh-density pixel-patterned MMIs have demonstrated analog and digital programmable beam steering and routing with few-micron footprints and minimal power penalty, mapped directly to “bitwise” logic at the photonic level (Delaney et al., 2021, Blundell et al., 2024).

6. Scalability, Design Tradeoffs, and Future Prospects

Scalability of NV-FPPGAs is governed by device/process limits, power budgeting, and architectural topology:

• Array Density and Fan-out: PCM and memresonator cells can be engineered to sub-20 μm footprints, resulting in $\gtrsim10^4$ elements/cm²; further scaling is limited by accumulated propagation loss, optical crosstalk, and control complexity (Tossoun et al., 2023, Blundell et al., 2024, Delaney et al., 2021).
• Power Budgeting: With essentially zero standby power, architectures leveraging PCM, ferroelectric memory, or MEMS latching decouple mesh scaling from static energy limits, supporting system-level arrays requiring only pulsed programming power on configuration (Catalá-Lahoz et al., 12 Jan 2026, Tao et al., 10 Jan 2026).
• Performance–Loss–Cyclability Tradeoff: Increasing PCM layer thickness or memresonator diameter enhances phase shift per length at the cost of optical loss and reduced multi-cycle robustness; device geometry and material stack optimization are central to performance (Blundell et al., 2024, Tossoun et al., 2023, Chen et al., 2023).
• Configuration Complexity: Multilevel and digital state space expansion places increased demands on control and calibration workflows, which is addressed by closed-loop, feedback-driven programming and scalable crossbar-style addressing.
• Integration and CMOS Compatibility: Monolithic co-integration with CMOS, adoption of FinFET-scale FeFETs, and 3D stacking of photonics/electronics herald further increases in mesh density and functional diversity (Tang et al., 2022, Tossoun et al., 2023).
• Emerging Directions: Ongoing work emphasizes further reduction of device size and IL (ultrathin PCM, subwavelength engineering), expansion to multi-wavelength/WDM arrays, and application-specific customization for quantum photonics, secure communications, and datacenter/networking platforms.

7. Notable Implementations and Research Trajectories

Multiple research groups have demonstrated key NV-FPPGA platforms:

• Sb$_2$Se$_3$ and Sb$_2$S$_3$ PCM Gate Arrays: Demonstrated by Delaney et al., Chen et al., and others, achieving ultralow loss ($<0.1$–0.5 dB), multi-level control, and direct-write pixel programmability (Delaney et al., 2021, Chen et al., 2023, Chen et al., 23 Jun 2025, Blundell et al., 2024).
• MEMS-Latching and Mechanically Programmable Circuits: Reported large-scale, robust, zero-power-hold operation and performed error-resilient configuration via swarm algorithms, matching analog mesh performance (Tao et al., 10 Jan 2026).
• Memresonator Hybrid III–V/Si Platforms: Heterogeneous integration yielding record-low energy, sub-ns phase shifters, and reconfigurable arrays for both switching fabrics and neuromorphic cores (Tossoun et al., 2023).
• Ferroelectric Silicon Photonic Mesh and FeFET-Driven Arrays: Si–BTO and FeFET-HZO devices have demonstrated 16-level, 1.25π multistate phase-shifter operation with sub-nW static power and full mesh (58+ PUC), paving the way toward fully CMOS-compatible non-volatile PICs (Catalá-Lahoz et al., 12 Jan 2026, Tang et al., 2022).
• NEO-PGA Electro-Optically Programmable Arrays: Demonstrated closed-loop, multi-bit control of Sb$_2$Se$_3$ PCM MZI meshes on a 300 mm silicon photonics platform, supporting high-dimensional switching, coupled-cavity physics, and robust mode sorting (Chen et al., 23 Jun 2025).

A plausible implication is that continued cross-fertilization between materials science (PCM, ferroelectric, MEMS), integrated photonic device design, and scalable electronic/photonics co-integration will accelerate the deployment of NV-FPPGAs for domain-specific and general-purpose optical information processing. These developments directly address the throughput, density, and energy limits underpinning next-generation optical computation, networking, and quantum circuitry.