Photonic Processors

• Photonic processors are integrated optical systems that manipulate coherent light signals to perform high-speed, energy-efficient computations.
• They employ advanced architectures such as MZI meshes and MRR arrays with multiplexing techniques like WDM and MDM for massive parallelism.
• Their applications range from real-time signal processing and neuromorphic AI acceleration to quantum computing and high-throughput imaging.

Photonic processors are integrated photonic systems engineered to perform high-speed information processing and computation using the manipulation of coherent optical signals. Unlike digital electronic processors, photonic processors exploit fundamental optical properties—such as high bandwidth, low propagation loss, massive parallelism through multiplexing, and sub-nanosecond latency—to address the intrinsic limitations of electron-based circuits in data throughput, energy efficiency, and latency for a diverse set of applications including communication, scientific computing, artificial intelligence, and quantum information processing.

1. Fundamental Architectures and Multiplexing Strategies

Photonic processors are realized as integrated circuits utilizing a variety of approaches for manipulating and routing light. Core architectures include reconfigurable mesh networks of Mach–Zehnder interferometers (MZIs), matrices of microring resonators (MRRs), cascaded directional couplers, programmable optical delay lines, and topological photonic crystals. A key enabler for processor scaling is the exploitation of multiplexing across multiple orthogonal photonic degrees of freedom:

• Wavelength-Division Multiplexing (WDM): Allows parallel processing of N independently modulated optical channels, each carried by a distinct wavelength, as in microring weight banks and microcomb-based processors.
• Mode-Division Multiplexing (MDM): Employs M co-propagating spatial modes within a waveguide as separate optical channels; on-chip mode multiplexers and demultiplexers realize efficient conversion between single-mode and multimode domains.
• Hybrid MDM×WDM: The total channel capacity becomes $C_{\mathrm{tot}}=M\times N$, enabling $M\times N$ independent operations within the same physical infrastructure. Recent hybrid processors integrate adiabatic directional couplers, multimode microring resonators, and balanced multi-mode photodetectors to fully exploit this scaling (Khaled et al., 2024).

Monolithic integration on silicon-on-insulator (SOI), silicon nitride (SiN), or other platforms enables massive device density, with recent advances incorporating phase-change materials (PCM), wafer-bonded ferroelectrics (e.g., PZT), or fully non-volatile, topologically protected photonic states for further scaling and robustness (Zhou et al., 5 Nov 2025).

2. Operating Principles, Mathematical Models, and Control

Photonic processors implement reconfigurable linear or nonlinear transformations on input optical signals, enabling vector–matrix multiplication (VMM), convolution, all-optical switching, and programmable filtering:

• Linear Transformation Meshes: Universal linear operations are performed by tuning cascaded arrays of MZIs, each parameterized by internal and external phases ($\theta$, $\phi$), to enact arbitrary $U(N)$ transformations. Decomposition algorithms (Clements, Reck) minimize optical depth and loss.
• Microring Weight Banks: Cascaded add–drop MRRs set the splitting ratio for particular wavelength channels, achieving signed weighting via balanced detection.
• Programmable Control: Phase shifts are controlled by integrated thermo-optic or electro-optic heaters, or by non-volatile phase change; device calibration involves LUT mapping of voltage (or current) to induced optical phase.

In hybrid WDM×MDM, each microring and photodetector is mode- and wavelength-specific; weight programming is achieved by thermal tuning, with current LUTs or feedback-optimized iterative algorithms. The overall signal flow combines input multiplexing, programmable photonic weight application, and fast detection/integration. Multimode or multiwavelength signals are optically summed or detected according to the processor design (Khaled et al., 2024, Zhu et al., 2 Apr 2025).

3. Key Performance Metrics

Photonic processors are characterized by a set of figures of merit reflecting their computational and physical capabilities:

• Processing Latency: Dominated by optical group delay through the processor (e.g., microring and photodetector response). Recent hybrid processors achieve $\tau_{\rm proc}\approx30$ ps or lower, orders of magnitude below electronic DSP latencies (Khaled et al., 2024).
• Computational Throughput: Expressed as the number of multiply-accumulate operations per second (MAC/s or OPS). For hybrid processors, throughput increases with channel count: $C_{\rm tot}=M \times N$, with aggregate photonic bandwidth $$B_{\rm ph}=N\,(\mathrm{channel\ spacing})\,\mathrm{us\;band}$$, and per-channel effective electrical bandwidth (e.g., up to 50 GHz/pin for balanced photodetectors).
• Energy Efficiency: Energy per operation ($E_{\mathrm{op}}$) achievable in state-of-the-art wafer-integrated topological photonic chips is $E_{\mathrm{op}} \approx 265$ fJ/OP, with compute densities exceeding 266 TOPS/mm$^2$ and aggregate photonic bandwidth of 0.8 Tbps (Zhou et al., 5 Nov 2025); such densities dramatically exceed even advanced thin-film lithium niobate or bulk silicon MZI meshes.
• Fidelity and Bit-Precision: Measured by amplitude or process fidelity of implemented linear transformations versus target; for matrix multipliers, bit-precision up to 10.7 bits for unitary and 7.32 bits for non-unitary operations has been demonstrated (Zhu et al., 2 Apr 2025).
• Loss, Crosstalk, and Thermal Stability: Insertion loss and inter-channel crosstalk directly impact SNR and scalability. Advanced SOI/SiN meshes routinely achieve losses per MZI <0.3 dB, total on-chip losses of 2.9–5 dB for $N\leq20$, crosstalk suppression of >21 dB, and negligible thermal cross-coupling with proper layout (Lu et al., 2023, Taballione et al., 2022).

Architecture	Compute Density (TOPS/mm$^2$)	Latency (ns/operation)	Energy/Op (fJ)
Topological PZT (2025)	266	<0.03 (30ps)	265
SOI MZI mesh (2025)	<2	0.03–0.1	1800–2500
TFLN mesh	0.02	0.1–1	8000–12000

4. Application Domains and Algorithmic Functionality

Photonic processors are deployed for a wide range of tasks:

• Signal Processing: Real-time optical MIMO signal unscrambling, RF phase-shift keying (PSK) unjamming, and high-dimensional optical fiber mode-scrambling/descrambling, with demonstrated operation at Gb/s–Tb/s rates and sub-50 ps latencies (Khaled et al., 2024, Lu et al., 2023).
• Neuromorphic and AI Acceleration: Demonstrated optical dot products, convolutions, and inference layers for neural networks (e.g., U-Nets, CNNs) at >93% classification accuracy on MNIST. TOPS-scale throughput engines have been integrated on SOI and via topological photonics; fully reconfigurable programmable meshes support both unitary and non-unitary multiplication (e.g., ONN layers, secure physical unclonable function computation) (Zhu et al., 2 Apr 2025, Zhou et al., 5 Nov 2025, Han et al., 19 Aug 2025).
• Domain-Specific Acceleration: Dedicated architectures can efficiently solve NP-complete problems such as Subset Sum and Exact Cover, leveraging passive mesh parallelism to explore all $2^N$ candidate solutions in a single optical pass, achieving $>$100× speedup vs. advanced CPUs for small $N$ (Xu et al., 2023, Han et al., 19 Aug 2025).
• Quantum Information Processing: Universal photonic processors realize arbitrary unitary transformations on $N$ spatial or frequency modes for quantum state evolution, programmable boson sampling, multi-photon entanglement routing, and quantum logic gates (e.g., 20-mode Si$_3$N$_4$ mesh with $F_{\text{Haar}} = 97.4\%$, $V_{\text{HOM}}=98\%$) (Taballione et al., 2022, Taballione et al., 2020, Pentangelo et al., 2023).
• Structured-Light and Imaging: Integrated processors reconstruct amplitude and phase of free-space optical beams, enabling real-time, compact OAM detection, super-resolution imaging, or quantum state characterization (Bütow et al., 2023).
• Real-Time Massive Parallel Processing: Microcomb-driven photonic processors achieve >10 Tb/s aggregate bandwidth, enabling concurrent execution of tens of video-processing functions (e.g., edge detection, motion blur) and processing hundreds of thousands of image streams in real time (Tan et al., 2024).

5. Reconfigurability, Programming, and Control Algorithms

Configuring photonic processors to perform diverse tasks requires precise, automated programming of tens to thousands of optical phase or amplitude elements:

• Calibration and Compilation: Modern processors deploy hierarchical, fully-automated test–compile–adjust (TCA) flows. High-level matrix (unitary or non-unitary) decompositions (e.g., Clements, diamond) map to phase settings, using hardware-specific LUTs for rapid translation of function to hardware parameters (Zhu et al., 2 Apr 2025).
• Feedback and Optimization: Reconfiguration is achieved via adjoint calibration metrics, direct fidelity evaluation, and gradient-based or black-box optimization routines (e.g., Nelder–Mead simplex), addressing phase ambiguity, thermal crosstalk, and sample-to-sample variations (Pentangelo et al., 2023).
• Self-Learning and Adaptive Operation: Processors integrating self-learning algorithms incrementally adjust phase settings via black-box gradient descent to maximize application-specific cost functions (e.g., channel correlation for MIMO, passband-stopband difference for filters, eye-opening for live signal correction). These routines demonstrate convergence to high-fidelity solutions across different functional regimes (Zhou et al., 2019).
• Programmability Range: Reconfigurable architectures support programmable matrix dimensions (from 1×1 up to 20×20), arbitrary hardware partitioning into concurrent computational blocks, and support for general-purpose and domain-specific computation on the same hardware instance (Dong et al., 30 Jan 2025, Han et al., 19 Aug 2025).

6. Scalability, Integration Challenges, and Future Directions

Scaling photonic processors involves challenges in device engineering, packaging, and system architecture:

• Photonic Density and Static Power: In dense PZT–SiN topological architectures, non-volatile phase programming and sub-µm component footprints enable >100× compute-density over MZI/SOI platforms. Zero static-power retention by ferro-electric or PCM tuning is key for scaling to multi-10$^3$–10$^4$ MAC/mm$^2$ (Zhou et al., 5 Nov 2025, Shafiee et al., 30 Oct 2025).
• Latency and Interconnects: Latency is constrained by optical path lengths, detector response, and electronic wiring capacitance. Optical-mode combining (MDM) eliminates wiring capacitance bottlenecks seen in spatial-multiplexed WDM schemes; photonic wire bonds and flip-chip integration allow for efficient electronic–photonic packaging (Khaled et al., 2024).
• Thermal Crosstalk and Device Yield: Enhanced layouts (e.g., air trenches, broadband DCs, narrowband tunable microheaters) suppress phase-to-phase cross-coupling. Calibration protocols and direct feedback correct for residual drift or device aging (Pentangelo et al., 2023).
• Power Scaling: Thermal tuning per ring or MZI ($\sim$10–50 mW) becomes limiting for multicore, multi-channel arrays. Next-generation processors aim to adopt MEMS micro-actuation, phase-change materials, Pockels-active ferroelectric films, or stress-optic elements to reduce reconfiguration energy to pJ or sub-pJ/operation (Zhou et al., 5 Nov 2025).
• Hybrid and Heterogeneous Approaches: Emerging designs combine in-memory photonic computing (e.g., photonic-electronic neural co-processors) for low-latency inference, leveraging photonics for first-layer processing and dense electronic arrays (e.g., PCM- or SRAM-based) for deep layers or high-precision accumulation (Brückerhoff-Plückelmann et al., 31 Oct 2025).

Technology	Static Power (mW/ Element)	Max Mode/Channel Count	On-chip MAC Density (TOPS/mm$^2$)	Reconfig. Speed
SOI (therm-optic)	10–50	10–100	<2	$0.1$–$10~\mu$s
PZT/Topological	<0.1 (non-volatile)	16–1000	266	<1 ns
PCM-based DCs	0 (holding)	10–1000	10–50	10 ns–1 ms

Future directions include co-integration of light sources, on-chip optical gain, large-scale photonic wire bonds for optical I/O, further scaling of mesh topologies, and full-stack software–hardware automation for end-to-end application deployment.

7. Comparative Analysis and Prospects

Photonic processors currently demonstrate clear advantages in bandwidth density, latency, and energy per operation over electrical and hybrid architectures, with application relevance accelerating in high-speed communication, AI/ML inference, domain-specific acceleration, quantum photonic computation, and high-throughput imaging applications.

• Bandwidth and Latency: Best-in-class processors achieve up to 17 Tb/s real-time ultrafast video signal processing and $\lesssim$0.2 pJ/operation, with true real-time, all-optical parallelism across up to $10^5$ video streams (Tan et al., 2024).
• Flexibility: Programmable, universal processor meshes support arbitrary $U(N)$ or $M\times N$ linear operations, vital for neuromorphic and quantum AI, as well as reconfigurable communications.
• Programmability: Automated electronic–photonic control software and self-learning update protocols enable months-long configuration stability paired with seconds-scale reconfiguration (Zhu et al., 2 Apr 2025, Pentangelo et al., 2023).
• Challenges: Device yield, total energy efficiency (esp. for tunable elements), loss management in large-meshes, and optical–electronic interface integration represent prevailing bottlenecks as processor footprints and complexity scale.

Photonic processors are thus central to the transition from application-specific signal-processing modules to universal, hyperscale, AI-enabled, and quantum-capable photonic computing platforms. The continuous refinement of topological design, non-volatile tuning, hybrid multiplexing, and automated calibration is projected to drive a new generation of large-scale, energy-proportional, and programmable photonic processors (Khaled et al., 2024, Zhou et al., 5 Nov 2025, Cataldo et al., 16 Sep 2025, Zhu et al., 2 Apr 2025, Brückerhoff-Plückelmann et al., 31 Oct 2025).