Photonics-Based MAC Operations

• Photonics-based MAC operations are architectures that use light's modulation, interference, and detection to perform vector dot products and matrix multiplications efficiently.
• These systems employ devices like E/O modulators, Mach–Zehnder interferometers, and microring resonators to encode data and programmable weights, enabling coherent and incoherent summation.
• Key benefits include massive parallelism, ultrafast speeds (10–100 GHz), and low energy per operation (10 fJ–2 pJ), with scalability through wavelength, time, or mode multiplexing.

Photonics-based multiply-accumulate (MAC) operations refer to hardware architectures that perform vector dot products and general matrix multiplications using the propagation, modulation, interference, and detection of optical signals. These architectures underpin photonic accelerators for machine learning, signal processing, and scientific computation, offering prospects for massive parallelism, ultrafast throughput, low latency, and reduced energy per operation relative to electronics.

1. Fundamental Physical Principles and Device Primitives

Photonics-based MAC exploits the linearity and parallelism of light to encode data (inputs), apply programmable weights, and sum the resulting products either coherently (via interference) or incoherently (via intensity summation):

• Data encoding is performed via electro-optic (E/O) modulation, mapping digital or analog inputs $x_i$ to the amplitude, phase, wavelength, or temporal structure of optical carriers (lasers, combs, or waveguide light).
• Weighting is realized by devices such as Mach–Zehnder interferometers (MZIs), microring resonators (MRRs), phase-change memory (PCM) absorbers, or spatial light modulators (SLMs), which modulate amplitude and/or phase in accordance with programmable weights $w_{ij}$.
• Multiplication occurs as each channel multiplies the data encoding $x_i$ with the weight $w_i$ through optical attenuation or phase shifting, or as a result of coherent or non-coherent mixing.
• Accumulation is effected by the photonic superposition of multiple weighted optical channels—either summed as optical intensities in photodetectors (non-coherent), or as field amplitudes with subsequent detection (coherent), yielding $\sum_i w_i x_i$ as a direct analog output.
• Detection and decoding converts the optical aggregate into an electrical signal using high-speed, low-noise photodetectors, often followed by analog or digital post-processing.

Distinct MAC architectures exploit different degrees of freedom: wavelength (WDM), time (TDM), mode (MDM), space (multiwaveguide), or combinations thereof (Sunny et al., 2021, Mojaver et al., 2024, Latifpour et al., 2023, Kim et al., 2024).

2. Circuit Architectures and Matrix Factorizations

Multiple architectural paradigms exist, each with trade-offs in scalability, performance, and compatibility with foundry technology:

• Interferometric Meshes: Arbitrary (unitary/non-unitary) transformations are realized via layered 2×2 beam-splitters or MZIs, as in Reck, Clements, or low-depth circular meshes. Interleaved layers of phase shifters and mixing blocks parameterize $U=\prod_{l} V^{(l)} \Phi^{(l)}$ for unitary or general matrices, sometimes extended via 2N×2N embeddings for non-unitary maps (Fldzhyan et al., 2024, Markowitz et al., 2023). This approach excels in universality, precision, and error-tolerance, attaining full programmability with depth $D=N+2$ for $N$-mode systems (Fldzhyan et al., 2024).
• MZI Meshes and SVD Decomposition: Programmable MZIs configured by singular-value decomposition or block matrices realize complex-valued MVMs with cascades of amplitude/phase masks interlaced with static mixing layers, e.g., $M = D^{(N+1)} F \cdots F D^{(1)}$ (Markowitz et al., 2023).
• Broadcast-and-Weight (B&W) WDM Banks: Each input $x_k$ is mapped to a distinct wavelength $\lambda_k$ and modulated in intensity or phase. After traversing programmable weight banks (MRRs or similar filters), all channels are multiplexed and summed in a broadband photodiode to yield the MAC result (Salmani et al., 2021, Sunny et al., 2021).
• Mode/TDM/Waveguide Multiplexing: Channels are separated by spatial waveguide, temporal pulses, or supported optical modes (TE, TM, higher-order). Recent schemes combine waveguide multiplexing and multiport detection for scalable, non-coherent MAC up to hundreds of channels (Tang et al., 2024, Chai et al., 30 Jan 2025).
• Field-Programmable In-Memory and SLM Architectures: Free-space or photonic-core architectures utilize SLMs, PCM phase-change arrays, or other memory media as high-bit-precision programmable elements, interfacing with spatial/frequency-encoded optical matrix operations (Latifpour et al., 2023, Feldmann et al., 2020).

3. Mathematical Models and Signal Pathways

Across architectures, MAC operations are consistently formulated as $y_i = \sum_{j=1}^N w_{ij} x_j$. The physical mapping depends on optical encoding, modulator transfer function, weight programming resolution, and summation modality:

• Modulation: $E_{\text{out},j} = w_{ij} E_{\text{in},j}$, or $P_{\text{out},j} = w_{ij} P_{\text{in},j}$ for amplitude encoding.
• Summation: Incoherently, $\sum_j w_{ij} P_{\text{in},j}$ detected linearly; coherently, the superposition $\left|\sum_j w_{ij} E_{\text{in},j}\right|^2$ is measured, enabling signed/complex weights but requiring phase stability.
• Layered matrix–vector product: Implemented via cascaded programmable layers (amplitude, phase, fixed unitaries), exploiting block-wise or recursive decompositions for non-unitary tasks (Markowitz et al., 2023, Fldzhyan et al., 2024).

Precision, speed, and fidelity are set by extinction ratio, crosstalk, photodetector responsivity, phase noise, and analog quantization steps in modulators or memory cells.

4. Performance Metrics and Scaling Laws

Photonics-based MAC implementations are characterized by high channel concurrency, massive bandwidth, and energy efficiency:

Metric	Range/State-of-Art	Notes
Bandwidth per MAC channel	10–100 GHz	Set by modulator, detector, waveguide bandwidth (Al-Qadasi et al., 2021)
Energy per MAC	10 fJ – 2 pJ	Material/device/design dependent; sub-pJ feasible (Sunny et al., 2021Najafi et al., 2024)
Compute density	>1 TOPS/mm²	Via multi-mode, WDM, spatial parallelism (Wang et al., 2024, Kim et al., 2024)
Matrix size scalability	$\sim$10² (integrated PIC)	Larger sizes: increased loss, complexity, calibration
Universality/Precision	$<$1e-7 relative error	With sufficient programmable layers (Markowitz et al., 2023)
Weight resolution	4–8 bits (thermo-optic/MRR)	Higher with PCM or SLM (Najafi et al., 2024, Latifpour et al., 2023)
Latency	10–100 ps per operation	Optical propagation + detection

Area and device count scale as $O(N^2)$ in mesh/topology-based architectures, but can be reduced by leveraging time, wavelength, or spatial multiplexing for $O(N)$ active elements (Chai et al., 30 Jan 2025).

5. Architectural Variants and Application Scenarios

Photonic MAC kernels are adapted for AI acceleration, signal processing, and scientific computing:

• Deep learning inference (DNN/ONN): Photonic tensor cores, often integrated with on-chip neural network layers, leverage passive or programmable weight banks (MRR, PCM, SLM) for high-throughput linear transformations (Feldmann et al., 2020, Peserico et al., 2022, Najafi et al., 2024).
• Massive MIMO communications: Ultra-fast matrix inversion and dot products accelerate baseband processing and channel decoding beyond digital ASIC limits (Hsueh et al., 2024, Salmani et al., 2021).
• Sensor-edge computing/IoT: Near-sensor MAC engines enable low-latency, energy-efficient inference, supporting neuro-symbolic architectures and hybrid symbolic reasoning (Najafi et al., 2024).
• All-optical systolic arrays: Designs with true output-stationary, all-optical dataflow support matrix–matrix products, e.g., for transformer attention (Kim et al., 2024).
• In-memory and free-space photonic computing: Hyperspectral, SLM-programmable systems combine frequency, space, and voltage-tunable optics to implement massive parallel MACs for large-dimension scientific/AI workloads (Latifpour et al., 2023).

6. Implementation Challenges, Error Sources, and Remedies

Major challenges include:

• Thermal crosstalk and drift: Stability of MRR resonance and phase shifters is impacted by temperature, requiring closed-loop calibration and sometimes real-time feedback (Sunny et al., 2021, Najafi et al., 2024).
• Component nonidealities: Limited extinction ratio, process variation, and insertion loss reduce analog fidelity; mitigation includes careful layout, heater design, and compensation algorithms (Al-Qadasi et al., 2021, Najafi et al., 2024).
• Crosstalk and scaling: WDM and mode multiplexing face fundamental limits from filter linewidth, channel separation, and modal orthogonality; spatial/waveguide multiplexing offers more favorable scaling for hundreds of channels (Tang et al., 2024).
• Precision and noise: Photodetector shot noise, device nonlinearity, and ADC/DAC quantization constrain the minimum bit precision; error is often tolerated with robust training or digital correction (Latifpour et al., 2023, Feldmann et al., 2020).
• Programming overhead: SLM and PCM schemes require relatively slow weight updates, but enable non-volatility and higher bit-depth; MRRs offer moderate-speed (μs–ms) reconfiguration (Mojaver et al., 2024, Najafi et al., 2024).
• Electronic–photonic interfacing: Data conversion and controller overheads remain significant for mixed-signal accelerators, motivating integration of photonic DACs/ADCs and co-design approaches (Hsueh et al., 2024).

Error tolerance is intrinsic to some mesh factorizations, notably the circular BS mesh, which demonstrates a flat-plateau response with respect to beam splitter parameter variation (Fldzhyan et al., 2024). In bandwidth-critical applications, analog photonic MACs provide throughput and latency unattainable in digital logic at comparable energy levels.

7. Outlook and Comparative Assessment

Photonics-based MAC engines promise a regime of computational density, energy efficiency, and latency inaccessible to purely electronic accelerators for moderate to large matrix sizes ($N\sim10^2$). Continued advances in ultra-low-loss waveguides, non-volatile memory materials, high-Q resonators, high-speed modulators, scalable multiport detectors, and robust calibration/control electronics are narrowing the gap with mature electronic integration (Al-Qadasi et al., 2021, Peserico et al., 2022, Wang et al., 2024, Latifpour et al., 2023).

Comparison to electronics shows photonic MACs already achieving $10\times$ to $100\times$ higher throughput and approaching (sub-)pJ/MAC energy; improvements in device precision and system-level integration are expected to further extend this lead (Sunny et al., 2021, Hsueh et al., 2024). The main limitations center on systemsize scalability, reconfigurability, and interface overheads. A plausible implication is that future AI, signal processing, and sensor-fusion workloads will deploy hybrid photonic–electronic or multi-modal photonic accelerators, leveraging the distinctive advantages of light to push beyond the fundamental limits of CMOS and von Neumann architectures.