Parallel Muon Reconstruction

• Parallel muon reconstruction is a high-energy detector technique that uses seeded Hough transforms and hardware-level parallelism to rapidly process muon tracks.
• The method employs a specialized Hough transform with vectorized least squares fitting to achieve precise momentum determination within microsecond latencies.
• Integration of ARM Cortex-A9 Neon SIMD and custom FPGA architectures ensures over 98% segment-finding efficiency and meets stringent first-level trigger timing requirements.

A parallel muon, in the context of high-energy collider detectors, refers to the processing and reconstruction of muon tracks in drift-tube chambers with substantial parallelism to meet stringent real-time trigger requirements. The implementation described in the ATLAS experiment at the High-Luminosity Large Hadron Collider (HL-LHC) is a paradigmatic example, leveraging both algorithmic methods and hardware-level parallel floating-point execution to rapidly identify muon trajectories and suppress background, achieving performance compatible with first-level trigger constraints (Abovyan et al., 2018).

1. Seeded Hough Transform for Track Reconstruction

The parallel muon reconstruction pipeline is built upon a Hough transform tailored for fast unidimensional scans, exploiting prior information from fast trigger chambers. In the ATLAS muon drift tube (MDT) system, the general Hough transform for lines in the $(x, y)$ plane is defined as:

$r = x\,\cos\theta + y\,\sin\theta$

Each detector hit $(x_i, y_i)$ casts a “vote” for all $(r, \theta)$ that satisfy this relation, such that straight tracks yield peaks in $(r, \theta)$ ("Hough space"). However, ATLAS leverages the fast trigger chambers (RPC/TGC) to provide a coarse estimate of the track slope $m \approx \tan\theta$ (with accuracy $\mathcal{O}(10\,\mathrm{mrad})$). The Hough transform is "seeded" at the approximate slope $\bar m$, requiring only the intercept $b$ of the linear trajectory to be scanned:

$y = m\,z + b$

For each MDT hit, the measured input includes the tube center $r = x\,\cos\theta + y\,\sin\theta$0, drift radius $r = x\,\cos\theta + y\,\sin\theta$1, and the seeded slope $r = x\,\cos\theta + y\,\sin\theta$2. Geometry yields two possible intercept solutions (for either side of the wire):

$r = x\,\cos\theta + y\,\sin\theta$3

Quantizing $r = x\,\cos\theta + y\,\sin\theta$4 to 1 mm and sorting all $r = x\,\cos\theta + y\,\sin\theta$5 values ($r = x\,\cos\theta + y\,\sin\theta$6 = number of hits), a histogram identifies clusters representing true track segments. The final segment fitting is performed by linearizing in $r = x\,\cos\theta + y\,\sin\theta$7 and $r = x\,\cos\theta + y\,\sin\theta$8, yielding $r = x\,\cos\theta + y\,\sin\theta$9 normal equations for least squares optimization over the selected hits.

2. SIMD Parallelization on ARM Cortex-A9 Neon

To meet latency constraints, parallelization is realized on the ARM Cortex-A9’s Neon Single Instruction Multiple Data (SIMD) engine, capable of 4-wide single-precision floating-point vector operations. Data are organized into 16 byte-aligned arrays:

• float r[16], z[16], y[16], sign[16]; (`sign = \pm 1$(x_i, y_i)$0b_{\pm}$)</li> </ul> <p>Constants$(x_i, y_i)$1 are precomputed per segment. The SIMD pipeline processes four hits per iteration, using vector instructions: $(r, \theta)$8 Each iteration comprises one vector load, a fused multiply–subtract, a multiply, a subtract, and a store. Memory alignment and prefetch intrinsics are employed to optimize throughput. The SIMD-enabled code delivers %%%%22$(r, \theta)$23%%%% speedup over scalar code, reducing the segment-fit time from $(x_i, y_i)$42 μs to $(x_i, y_i)$50.5 μs per segment.

  3. Integrated Detector Hardware Architecture

  The processing pipeline is tightly coupled with the detector’s hardware:

  • Xilinx Zynq XC7Z045 SoC integrates dual 800 MHz Cortex-A9 CPUs and FPGA fabric.
  • On-chamber electronics forward hits through optical GBT links to off-detector "hit-matcher" FPGA, with custom logic including 8k-deep input FIFO and multiple data-shuffling FIFOs.
  • The hit matcher associates MDT hits with L0 pretriggers, streaming matched hits (up to 16 per chamber) to segment-reconstruction FPGA IP over AXI4-Stream at 320 MHz.
  • The segment-reconstruction IP (pattern recognition and bubble-sort clustering) interrupts the ARM CPU via IRQ, delivering input segments over a 32-bit AXI FIFO.
  • The ARM CPU reads segment candidates, executes the vectorized least squares fit, and performs momentum determination, typically in $(x_i, y_i)$6500 ns.

  4. Detailed Latency Breakdown

  The real-time constraints are governed by the following latency budget (in nanoseconds):

  Step	Latency (ns)
  Time of flight ($(x_i, y_i)$7MDT)	65
  Maximum drift time	750
  Digitization & on-chamber multiplexing	561
  Optical link (max 100 m fibre)	516
  Hit matching (PL IP)	440
  Transfer to segment-recognition IP	250
  Pattern recognition (Hough clustering)	204
  Transfer cluster to ARM (AXI)	60
  ARM segment-fit (Neon SIMD)	500
  Transfer back segment params	250
  Momentum determination	80
  Total	≈3,630

  The total cumulative latency for the MDT-based parallel muon reconstruction is thus approximately $(x_i, y_i)$8s. This fits comfortably within the 10 μs L0 trigger budget at the HL-LHC.

  5. Test-Beam Results and Scalability Prospects

  Performance validation at CERN’s Gamma Irradiation Facility demonstrates segment-finding efficiency exceeding 98% at hit background rates up to 200 kHz/tube. The MDT-trigger momentum resolution is $(x_i, y_i)$9 at $(r, \theta)$0, a substantial improvement from $(r, \theta)$1 using only trigger chambers. Throughput analysis shows processing time per segment $(r, \theta)$2s, supporting $(r, \theta)$33 million segments/s per ARM core. The Neon-optimized implementation runs four times faster than scalar code, and six Zynq SoCs per spectrometer sector (two per chamber layer) can sustain up to 3 kHz of pretriggers with margin.

  6. Implications for HL-LHC Muon Trigger and Future Directions

  The parallel muon reconstruction method enables sharp momentum thresholding in the ATLAS L0 trigger, with the $(r, \theta)$4s MDT-based momentum refinement efficiently suppressing low-$(r, \theta)$5 backgrounds by an order of magnitude. The approach improves the $(r, \theta)$6 turn-on curve and fits within existing L0 latency budgets. Further gains could plausibly be achieved with wider vector pipelines (e.g., ARMv8 Neon) or utilization of embedded FPUs in more advanced SoCs, potentially decreasing total latency below $(r, \theta)$7s or further increasing throughput.

  A plausible implication is the adopted parallel muon processing architecture, combining algorithmic seeding and SIMD acceleration, sets a scalable template for future detector upgrades at even higher luminosities or for integration with more compute-intensive reconstruction algorithms.