Race-Track Trapped-Ion Quantum Processor

• Race-track trapped-ion quantum processors are defined by ring-shaped ion traps with periodic boundaries that enable continuous, scalable quantum operations.
• They integrate advanced photonic networks and optimized ion-shuttling protocols to achieve low-error rates (10⁻⁴–10⁻³) and high-fidelity gate operations.
• System-level benchmarking and scheduling optimizations demonstrate reduced operation times and enhanced parallelism, supporting fault-tolerant quantum computing.

A race-track trapped-ion quantum processor is a quantum charge-coupled device (QCCD) architecture wherein surface-electrode ion traps are physically arranged in a closed-loop ("race track" or ring) geometry, with periodic or rotational boundary conditions. This configuration enables scalable transport and control of ions across multiple zones for quantum information processing. The architecture incorporates advanced techniques such as electrode broadcasting, integrated photonics, multi-zone operation, and scheduling optimizations. Recent experiments have demonstrated race-track devices with up to 98 qubits, error rates at or below the 10⁻⁴−10⁻³ level, efficient ion shuttling, low crosstalk, and successful implementations of complex quantum algorithms and benchmarks encompassing system-level performance and scalability (Moses et al., 2023, Mordini et al., 2024, Ransford et al., 7 Nov 2025, Jang et al., 13 Jan 2026, Pino et al., 2020, Taniguchi et al., 21 Sep 2025).

1. Trap Geometry and Electrode Configurations

The race-track architecture employs segmented surface-electrode traps formed into a closed ring with periodic boundary conditions, facilitating continuous ion circulation and enabling robust transport protocols.

• Trap Layout: Two concentric RF electrodes (inner: +VRF, outer: −VRF) create an RF null at heights typically around 70–82 μm above the surface. Zones are spaced regularly (e.g., 375–750 μm) around the ring and function as quantum gate regions, storage domains, or reorder-only locations (Moses et al., 2023, Ransford et al., 7 Nov 2025).
• Electrode Pattern: Multiple DC control electrodes are tiled between RF rails, with multi-layer metallization used to route RF beneath the active surface, preserving uninterrupted trap geometry. Electrode widths typically range from 50–120 μm, and zones often consist of stacks of 10–16 DC segments per branch (Taniguchi et al., 21 Sep 2025, Mordini et al., 2024).
• Junctions and Branches: In ring-plus-junction architectures, X-junctions act as intersections for random-access ion routing. In 3D-printed micro-junction designs, diamond-shaped overhanging RF rails are suspended above planar DC electrodes, and optimized fillets/offsets dramatically lower the pseudopotential barrier for crossing, improving motional coherence (Taniguchi et al., 21 Sep 2025).
• Electrode Broadcasting: Certain implementations use “ABC tiling,” wiring storage DC electrodes in repeating groups for conveyor transport; fast shuttling and batch transport primitives are realized by moving ions along these segmented electrodes using phase-shifted voltage sets (Moses et al., 2023).

2. Integrated Photonics and Optical Networks

Advanced ion control is achieved by integrating photonic components on-chip, delivering optical fields to each zone via buried waveguide networks.

• Waveguide Technology: Si₃N₄ waveguides (TriPleX platform) are buried under SiO₂ and routed to chip edges, with coupling efficiencies ≈70% into external fiber arrays. Each zone is equipped with phase-locked grating couplers for 729 nm gate light and single 854/866 nm repump couplers (Mordini et al., 2024).
• Light Routing and Control: Individual input fibers are split on-chip to address all zones, with external acousto-optic modulators (AOMs) allowing independent amplitude and frequency modulation for each branch. This network supports scalable qubit addressing by extending fiber splitters or adding waveguide Y-junctions and further AOM-TA chains (Mordini et al., 2024).
• Standing-Wave Control: Plane waves from closely spaced couplers create standing wave patterns at the ion height, allowing precise spatial addressing and phase control for the targeted transition (e.g., Ca⁺ at 729 nm) (Mordini et al., 2024).
• Scaling Challenges: Long-term stability of photonic phases across many zones demands solutions such as Mach–Zehnder referencing, active fiber phase-noise cancellation, or encoding of qubit phases in memory levels. Integration of UV/blue waveguides for cooling remains under development (Mordini et al., 2024).

3. Ion Shuttling Protocols, Motional Excitation, and Crosstalk

High-performance quantum processing depends on fast and low-heating ion transport between zones, as well as stringent mitigation of spurious motional excitation and optical crosstalk.

• Transport Waveform Design: Time-dependent voltages on DC electrodes are computed via quadratic programming, ensuring potentials track moving harmonic wells or double-well transitions for crystal split/merge operations. Filtering constraints and amplitude bounds are included to avoid waveform distortion (Pino et al., 2020, Mordini et al., 2024).
• Speed and Heating: Typical inter-zone shuttling times are 200–283 μs for 375–750 μm separation, with motional excitation after optimal compensation reduced to |α|²≈8 quanta (coherent) and negligible incoherent heating (Mordini et al., 2024, Pino et al., 2020, Ransford et al., 7 Nov 2025). In 3D-junction devices, crossing barriers are as low as 7 meV, yielding total excitation per round-trip of ≈1.9×10⁻⁴ quanta (Taniguchi et al., 21 Sep 2025).
• Charging Mitigation: Stray charge from exposed dielectrics (grating cutouts) is modeled and compensated by fitting additional fictitious electrode potentials to sideband spectroscopy data, enabling uniform trap frequency and minimized transport heating (Mordini et al., 2024).
• Crosstalk Performance: Measured optical crosstalk between adjacent zones is R_ct≈0.14% (Ω_off/Ω_on), corresponding to ≤10⁻⁶ in power. Simultaneous multi-zone operations show sub-percent crosstalk; mid-circuit detection crosstalk can be <1% when spatially isolated (Mordini et al., 2024, Pino et al., 2020).
• Field Noise Correlation: Ramsey spectroscopy in separate zones yields correlation coefficients R≈0.996, validating shared stabilization schemes (Mordini et al., 2024).

4. Gate Operations and System-Level Benchmarking

Race-track processors support high-fidelity single- and two-qubit gates with measured performance spanning randomized benchmarking, quantum volume, and algorithmic demonstrations.

• Qubit Transitions: Typical choices are electric-quadrupole transitions (e.g., Ca⁺: 4S₁/₂↔3D₅/₂) or hyperfine “clock” states (e.g., Yb⁺, Ba⁺). Zone-local control Hamiltonians are of the form $$H_I = \hbar\Omega(\sigma^+e^{i(\Delta k\cdot x-\delta t)} + h.c.)$$, with zone-dependent Rabi frequency Ω determined by local field and matrix element (Mordini et al., 2024).
• Gate Fidelity Metrics:
  • Single-qubit gates: errors 1.1×10⁻⁴–2.5×10⁻⁵ (Moses et al., 2023, Ransford et al., 7 Nov 2025, Pino et al., 2020).
  • Two-qubit gates (e.g., Mølmer–Sørensen, $U_{ZZ}$): errors 7.9×10⁻³–7.9×10⁻⁴ (Moses et al., 2023, Ransford et al., 7 Nov 2025, Pino et al., 2020).
  • SPAM error: as low as 4.8×10⁻⁴–1.6×10⁻³ per qubit (Moses et al., 2023, Ransford et al., 7 Nov 2025).
• Benchmarking Protocols: Mirror benchmarking, linear cross-entropy benchmarking (XEB), and quantum volume (e.g., QV=2¹⁶ for 32 qubits and QV=64 for six qubits) are used for system-level characterization (Moses et al., 2023, Pino et al., 2020). 32-qubit GHZ states achieved fidelities F=0.82(1)–0.74(1) (Moses et al., 2023).
• Algorithmic Demonstrations: Quantum Approximate Optimization Algorithm (QAOA), Hamiltonian simulation, repetition code error correction, and dynamic simulations (HoloQUADS) have been run on up to 32 qubits, showing optimal cut values and exponential suppression of logical errors with code distance (Moses et al., 2023).

5. Parallelism, Scheduling, and Throughput Optimization

Maximizing hardware parallelism, optimizing scheduling, and reducing ion circulation overhead are critical for efficient circuit execution.

• Zone Parallelism: Devices like Helios offer up to eight quantum-logic zones for simultaneous 1Q and 2Q gate execution. System clock time for a full circuit layer on 98 qubits is ≈55 ms, with two-qubit gate throughput up to ≈890 gates/s (Ransford et al., 7 Nov 2025).
• Baseline Scheduling (“Rolodex” Model): Circuits are grouped into depth-layers; batches of gates are executed in parallel across available zones, followed by a full-lap ion circulation ("Rolodex"). Runtime $$T_\mathrm{total}^{\mathrm{Rolodex}}=\sum_i[T_\mathrm{gate}^{(i)}+T_\mathrm{circ}(Z)]$$, where $T_\mathrm{circ}(Z)\propto Z$ causes a U-shaped scaling with optimal zone number (Jang et al., 13 Jan 2026).
• Optimization Strategies (Plutarch): Three approaches mitigate scaling bottlenecks (Jang et al., 13 Jan 2026):
  1. Unitary decomposition and translation: Balanced-tree CX chains translated to native $R_{ZZ}(\alpha)$ gates reduce shuttling and gate depth.
  2. In-place block scheduling: Execution prioritization of nearby gates within zones minimizes full-circuit circulation.
  3. Physical shortcuts: Adding nonadjacent “shortcut” paths between zones reduces worst-case travel by up to 50%.

• Empirical Impact: Plutarch yields monotonic runtime reductions with zone scaling ($T_\mathrm{Plutarch}(Z)$), avoiding slowdowns observed in naive parallelism, and achieves up to 66% speedup in 32-qubit variational workloads, as well as 32–53% reductions in QAOA and distillation tasks when shortcuts are implemented (Jang et al., 13 Jan 2026).

6. Scalability, Error Mitigation, and Future Prospects

Race-track QCCD processors address the scaling requirements for fault-tolerant quantum computing by combining modularity, optimized transport, and integrated control systems.

• Scalability Mechanisms: Modular ring/junction network architectures, 3D-printed junction arrays, and integrated photonic modules each support straightforward extension to dozens or hundreds of zones (Taniguchi et al., 21 Sep 2025, Ransford et al., 7 Nov 2025, Mordini et al., 2024).
• Error Budget: Dominant gate infidelity sources include spontaneous emission, laser-phase noise, heating during transport/gate, and voltage noise. Typical U_{ZZ} error budgets: <8.2×10⁻³, with position fluctuation contributing most (Pino et al., 2020).
• Heating and Compensation: Cryogenic operation (50 K–4 K) combined with active charging mitigation, stray-field compensation, and argon-ion-beam cleaning reduce anomalous heating rates and preserve motional coherence (Taniguchi et al., 21 Sep 2025, Mordini et al., 2024).
• Future Directions: Development areas include full parallelization across all gate-zone rows, higher zone counts, on-chip electronic control (cryo-CMOS, multichannel DACs), integration of photonics for all wavelengths (including UV/blue for cooling), hybrid optical→memory encoding for phase control, and modular multi-chip assemblies for scaling >100 qubits (Moses et al., 2023, Mordini et al., 2024, Ransford et al., 7 Nov 2025).
• Fault Tolerance: The combination of low two-qubit gate error, configurable connectivity, and robust transport supports quantum error correction (QEC) block implementations (Moses et al., 2023, Pino et al., 2020).

7. Materials, Fabrication, and Error Sources in 3D-Printed Architectures

Three-dimensionally structured ion traps introduce significant advances in junction performance and modularity but require precise materials engineering and rigorous error mitigation.

• Material Properties: IP-Dip photoresist core for 3D printing, coated with Ti/Au for conductivity, yields RMS surface roughness <30 nm. Geometric tolerances are maintained within ±200 nm height and ±100 nm edge radius (Taniguchi et al., 21 Sep 2025).
• Junction Optimization: By introducing vertical deflections at strategic locations (O₁, O₂), the junction pseudopotential barrier is reduced from ≈65 meV (planar) to ≲7 meV (3D), facilitating low-heating fast transport (75 μs per crossing, excitation <2×10⁻⁴ quanta) (Taniguchi et al., 21 Sep 2025).
• Error Sources: Heating from surface noise, RF noise, stray fields, and fabrication variances are dominant. Mitigation includes cryogenic cooling, in-situ surface cleaning, active compensation, and feedback control of RF amplitudes (Taniguchi et al., 21 Sep 2025).
• Scalability: Modular assembly via flip-chip connectors and daisy-chained branch modules supports large arrays. Control software indexes zones for flexible operation across extended networks (Taniguchi et al., 21 Sep 2025).

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Race-track trapped-ion processors represent the intersection of scalable trap geometry, photonic integration, advanced control theory, and system-level optimization, and form the basis for current and next-generation quantum computers operating at gate fidelities approaching the thresholds required for fault-tolerant quantum error correction (Moses et al., 2023, Mordini et al., 2024, Ransford et al., 7 Nov 2025, Jang et al., 13 Jan 2026, Pino et al., 2020, Taniguchi et al., 21 Sep 2025).